Voltage regulating circuit for a capacitive load

专利名称：Voltage regulating circuit for a capacitive

load

发明人：Khouri, Osama,Micheloni, Rino,Motta,

Ilaria,Torelli, Guido

申请号：EP99830418.2申请日：19990630公开号：EP1065580B1公开日：20031112

摘要：A voltage regulating circuit for a capacitive load, being connected between firstand second terminals of a supply voltage generator (VDD,GND) and having an inputterminal (IN) and an output terminal (OUT), comprises an operational amplifier (OP)having an inverting (-) input terminal connected to the input terminal (IN) of theregulating circuit and a non-inverting (+) input terminal connected to an intermediatenode of a voltage divider (R1,R2) which is connected between an output node connectedto the output terminal (OUT) of the regulating circuit and the second terminal (GND) ofthe supply voltage generator, and having an output terminal connected, for driving a firstfield-effect transistor (MPU), between the output node and the first terminal (VDD) ofthe supply voltage generator, the output terminal of the operational amplifier beingfurther connected to the output node through a compensation network (COMP), andcomprises a second field-effect transistor (MPD1) connected between the output nodeand the second terminal of the supply voltage generator (GND) and having its gateterminal connected to a constant voltage generating circuit means (RB,CB,MB,IB).

申请人：ST MICROELECTRONICS SRL

地址：IT

国籍：IT

代理机构：Botti, Mario

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