HY57V561620C(L)T(P)
4 Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applicationswhich require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16. HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputsare synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All inputand output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated bya single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read orwrite cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read orwrite command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•••
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interfaceJEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch (Leaded Package or Lead Free Package)
All inputs and outputs referenced to positive edge of system clock
Data mask function by UDQM, LDQMInternal four banks operation
••••
Auto refresh and self refresh8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
••
ORDERING INFORMATION
Part No.
HY57V561620C(L)T(P)-6HY57V561620C(L)T(P)-7HY57V561620C(L)T(P)-KHY57V561620C(L)T(P)-HHY57V561620C(L)T(P)-8HY57V561620C(L)T(P)-PHY57V561620C(L)T(P)-SNote :
1. HY57V561620CT Series : Nomal power & Leaded 54Pin TSOP II2. HY57V561620CLT Series : Low power & Leaded 54Pin TSOP II3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II
Clock Frequency
166MHz143MHz133MHz133MHz125MHz100MHz100MHz
PowerOrganizationInterface400mil 54pin TSOP II
(Normal)
/
Low Power
4Banks x 4Mbits x16LVTTL
(Leaded)
/
Lead Free
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility foruse of circuits described. No patent licenses are implied.
Rev. 0.5 / June 2004 1
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HY57V561620C(L)T(P)
PIN CONFIGURATION
VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7VDDLDQM/WE/CAS/RAS/CSBA0BA1A10/APA0A1A2A3VDD12345678910111213141516171819202122232425262754pin TSOP II400mil x 875mil0.8mm pin pitch545352515049484746454443424140393837363534333231302928VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8VSSNCUDQMCLKCKEA12A11A9A8A7A6A5A4VSSPIN DESCRIPTION
PINCLKCKECSBA0, BA1A0 ~ A12
ClockClock EnableChip SelectBank AddressAddress
Row Address Strobe, Column Address Strobe, Write Enable
Data Input/Output MaskData Input/OutputPower Supply/GroundData Output Power/GroundNo Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQMSelects bank to be activated during RAS activitySelects bank to be read/written during CAS activityRow Address : RA0 ~ RA12, Column Address : CA0 ~ CA8Auto-precharge flag : A10
RAS, CAS and WE define the operationRefer function truth table for details
Controls output buffers in read mode and masks input data in write modeMultiplexed data input / output pin
Power supply for internal circuits and input buffersPower supply for output buffersNo connection
RAS, CAS, WEUDQM, LDQMDQ0 ~ DQ15VDD/VSSVDDQ/VSSQNC
Rev. 0.5 / June 2004 2
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HY57V561620C(L)T(P)
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Synchronous DRAM
Self Refresh Logic& TimerInternal Row CounterCLKRow Active4Mx16 Bank 3CKECSRASCASWEUDQMLDQMRow PreDecoders4Mx16 Bank 2X decoders4Mx16 Bank 1X decoders4Mx16 Bank 0State MachineColumnActiveX decodersDQ0DQ1Sense AMP & I/O GateX decodersMemoryCellArrayI/O Buffer & LogicColumn PreDecodersY decodersDQ14DQ15Bank SelectColumn AddCounterA0A1AddressRegisterAddress buffersA12BA0BA1Mode RegistersBurstCounterCAS LatencyData Out ControlPipe Line ControlRev. 0.5 / June 2004 3
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HY57V561620C(L)T(P)
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient TemperatureStorage Temperature
Voltage on Any Pin relative to VSSVoltage on VDD relative to VSSShort Circuit Output CurrentPower Dissipation
Soldering Temperature ⋅ Time
TATSTGVIN, VOUTVDD, VDDQIOSPDTSOLDER
Symbol
0 ~ 70-55 ~ 125-1.0 ~ 4.6-1.0 ~ 4.6501260 ⋅ 10
Rating
°C°CVVmAW°C ⋅ Sec
Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Power Supply VoltageInput High VoltageInput Low Voltage
SymbolVDD, VDDQVIHVIL
Min3.02.0- 0.3
Typ.3.33.00
Max3.6VDDQ + 0.3
0.8
UnitVVV
Note11,21,3
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level VoltageInput Rise / Fall Time
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
SymbolVIH / VILVtriptR / tFVoutrefCL
Value2.4/0.41.411.450
UnitVVnsVpF
1Note
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit
Rev. 0.5 / June 2004 4
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HY57V561620C(L)T(P)
CAPACITANCE (TA=25°C, f=1MHz)
-6/7/K/H
Parameter
Input capacitance
CLK
A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM
Data input / output capacitance
DQ0 ~ DQ15
Pin
Symbol
Min
CI1CI2CI/O
2.52.54.0
Max3.53.86.5
Min2.52.54.0
Max4.05.06.5
pFpFpF
-8/P/S
Unit
OUTPUT LOAD CIRCUIT
Vtt=1.4VRT=250 ΩOutputOutput50pF50pFDC Output Load CircuitAC Output Load CircuitDC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Input Leakage CurrentOutput Leakage CurrentOutput High VoltageOutput Low Voltage
ILIILOVOHVOL
Symbol
Min.-1-12.4-Max11-0.4
UnituAuAVV
Note12
IOH = -4mAIOL = +4mA
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.5 / June 2004 5
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HY57V561620C(L)T(P)
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Speed
Parameter
Symbol
Test Condition
-6
Operating Current
Precharge Standby Current in Power Down Mode
IDD1IDD2PIDD2PS
Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mACKE ≤ VIL(max), tCK = 15nsCKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15nsInput signals are changed one time during 30ns. All other pins ≥ VDD-0.2V or ≤ 0.2VCKE ≥ VIH(min), tCK = ∞Input signals are stable.CKE ≤ VIL(max), tCK = 15nsCKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15nsInput signals are changed one time during 30ns. All other pins ≥ VDD-0.2V or ≤ 0.2VCKE ≥ VIH(min), tCK = ∞Input signals are stable.tCK ≥ tCK(min), IOL=0mAAll banks active
tRRC ≥ tRRC(min), All banks activeCKE ≤ 0.2V
1.5
mA
4
150220
130220
130220
130
Unit
-7110
Note
-K110
-H1102
-8100
-P100
-S100
mA
1
mA
1
IDD2N
Precharge Standby Current in Non Power Down Mode
IDD2NS
Active Standby Current in Power Down Mode
IDD3PIDD3PS
20
mA
103
mA
3
IDD3N
Active Standby Current in Non Power Down Mode
IDD3NS
Burst Mode Operating Current
Auto Refresh CurrentSelf Refresh Current
30
mA
25
IDD4IDD5IDD6
1302203
130200
110200
110200
mAmAmA
123
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II3.HY57V561620CT(P)-6/7/K/H/8/P/S4.HY57V561620CLT(P)-6/7/K/H/8/P/S
Rev. 0.5 / June 2004 6
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HY57V561620C(L)T(P)
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6
Parameter
Symbol
Min
CAS Latency = 3CAS Latency = 2
tCK3tCK2tCHWtCLWtAC3tAC2tOHtDStDHtAStAHtCKStCKHtCStCHtOLZ
6
1000
7.52.52.5--2.71.50.81.50.81.50.81.50.812.72.7
--5.46----------5.45.4
102.52.5--2.71.50.81.50.81.50.81.50.812.72.7
--5.46----------5.45.4
Max
Min7
1000
7.52.52.5--2.71.50.81.50.81.50.81.50.812.72.7
--5.45.4----------5.45.4
Max
Min7.5
1000
102.52.5--2.71.50.81.50.81.50.81.50.812.73
--5.46----------5.46
Max
Min7.5
1000
1033--321212121133
--66----------66
Max
Min8
1000
1033--321212121133
--66----------66
Max
Min10
1000
1233--321212121133
--66----------66
Max
Min10
1000
nsnsnsns
2
CAS Latency = 2nsnsnsnsnsnsnsnsnsnsnsnsns
1111111111
Max
ns
-7
-K
-H
-8
-P
-S
UnitNote
System Clock
Cycle Time
Clock High Pulse WidthClock Low Pulse Width
Access Time From Clock
CAS Latency = 3
Data-Out Hold TimeData-Input Setup TimeData-Input Hold TimeAddress Setup TimeAddress Hold TimeCKE Setup TimeCKE Hold TimeCommand Setup TimeCommand Hold Time
CLK to Data Output in Low-Z TimeCLK to Data Output in High-Z Time
CASLatency=3tOHZ3CASLatency=2tOHZ2
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.5 / June 2004 7
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HY57V561620C(L)T(P)
AC CHARACTERISTICS II
-6
Parameter
Symbol
Min
Operation
RAS Cycle Time
Auto Refresh
RAS to CAS Delay RAS Active TimeRAS Precharge Time
RAS to RAS Bank Active DelayCAS to CASDelay
Write Command to Data-In DelayWriteRecoveryTime
Data-IntoActiveCommandDQM to Data-Out Hi-ZDQMtoData-InMaskMRStoNewCommand
CAS Latency = 3CAS Latency = 2
tRRCtRCDtRAStRPtRRDtCCDtWTLtWRtDALtDQZtDQMtMRDtPROZ3tPROZ2tPDEtSREtREF
601842181210252023211---100K-------------64
601842181410252023211---100K-------------64
601545151510252023211---100K-------------64
652045201510252023211---100K-------------64
682048201610252023211---100K-------------64
702050202010252023211---100K-------------64
702050202010252023211---100K-------------64
nsnsnsnsnsCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKms
1
tRC
60
Max-Min60
Max-Min60
Max-Min65
Max-Min68
Max-Min70
Max-Min70
Max-ns
-7
-K
-H
-8
-P
-S
Unit
Note
Precharge to Data Output Hi-Z
PowerDownExitTimeSelfRefreshExitTimeRefresh Time
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.5 / June 2004 8
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HY57V561620C(L)T(P)
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage(V)3.453.33.02.62.42.01.81.651.51.41.00
0-21.1-34.1-58.7-67.3-73-77.9-80.8-88.6-93100MHz(Min)I(mA)
100MHz(Max)I(mA)-2.4-27.3-74.1-129.2-153.3-197-226.2-248-269.7-284.3-344.5-502.4
-0.7-7.5-13.3-27.5-35.5-41.1-47.9-52.4-72.5-9366MHz(Min)I(mA)
66MHz and 100MHz Pull-up00-100-2000.511.522.533.5I (mA)-300-400-500-600Voltage (V)IOH Min (100MHz)IOH Min (66MHz)IOH Max (66 /100MHz)IOL Characteristics (Pull-down)
Voltage(V)00.40.650.851.01.41.51.651.81.953.03.45
100MHz(Min)I(mA)027.541.851.658.070.772.975.477.077.680.381.4
100MHz(Max)I(mA)070.2107.5133.8151.2187.7194.4202.5208.6212.0219.6222.6
66MHz(Min)I(mA)017.7
66MHz and 100MHz Pull-down25020015010050000.511.522.533.5Voltage (V)IOL Min (100MHz)IOL Min (66MHz)IOL Max (100MHz)33.337.646.648.049.550.751.554.254.9
Rev. 0.5 / June 2004 9
I (mA)26.9
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HY57V561620C(L)T(P)
DEVICE OPERATING OPTION TABLE
HY57V561620C(L)T(P)-6
CAS Latency
166MHz(6ns)143MHz(7ns)133MHz(7.5ns)3CLKs3CLKs2CLKstRCD3CLKs3CLKs3CLKstRAS7CLKs6CLKs6CLKstRC10CLKs9CLKs9CLKstRP3CLKs3CLKs3CLKstAC5.4ns5.4ns5.4nstOH2.7ns2.7ns2.7nsHY57V561620C(L)T(P)-7
CAS Latency
143MHz(7ns)133MHz(7.5ns)125MHz(8ns)3CLKs2CLKs3CLKstRCD3CLKs3CLKs3CLKstRAS6CLKs6CLKs6CLKstRC9CLKs9CLKs9CLKstRP3CLKs3CLKs3CLKstAC5.4ns5.4ns6nstOH2.7ns2.7ns3nsHY57V561620C(L)T(P)-K
CAS Latency
133MHz(7.5ns)125MHz(8ns)100MHz(10ns)2CLKs3CLKs2CLKstRCD2CLKs3CLKs2CLKstRAS6CLKs6CLKs5CLKstRC8CLKs9CLKs7CLKstRP2CLKs3CLKs2CLKstAC5.4ns6ns6nstOH2.7ns3ns3nsHY57V561620C(L)T(P)-H
CAS Latency
133MHz(7.5ns)125MHz(8ns)100MHz(10ns)3CLKs3CLKs2CLKstRCD3CLKs3CLKs2CLKstRAS6CLKs6CLKs5CLKstRC9CLKs9CLKs7CLKstRP3CLKs3CLKs2CLKstAC5.4ns6ns6nstOH2.7ns3ns3nsHY57V561620C(L)T-8
CAS Latency
125MHz(8ns)100MHz(10ns)83MHz(12ns)3CLKs2CLKs2CLKstRCD3CLKs2CLKs2CLKstRAS6CLKs5CLKs4CLKstRC9CLKs7CLKs6CLKstRP3CLKs2CLKs2CLKstAC6ns6ns6nstOH3ns3ns3nsHY57V561620C(L)T(P)-P
CAS Latency
100MHz(10ns)83MHz(12ns)66MHz(15ns)2CLKs2CLKs2CLKstRCD2CLKs2CLKs2CLKstRAS5CLKs5CLKs4CLKstRC7CLKs7CLKs6CLKstRP2CLKs2CLKs2CLKstAC6ns6ns6nstOH3ns3ns3nsHY57V561620C(L)T(P)-S
CAS Latency
100MHz(10ns)83MHz(12ns)66MHz(15ns)3CLKs2CLKs2CLKstRCD2CLKs2CLKs2CLKstRAS5CLKs5CLKs4CLKstRC7CLKs7CLKs6CLKstRP2CLKs2CLKs2CLKstAC6ns6ns6nstOH3ns3ns3nsRev. 0.5 / June 2004 10
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HY57V561620C(L)T(P)
COMMAND TRUTH TABLE
Command
Mode Register SetNo OperationBank ActiveRead
H
Read with AutoprechargeWrite
H
Write with AutoprechargePrecharge All Banks
H
Precharge selected BankBurst StopDQMAuto Refresh
Burst-Read-Single-WRITE
Entry
Self Refresh1
Exit
HHHHHL
HXLH
LH
Entry
Precharge power down
Exit
L
H
LH
Clock Suspend
EntryExit
HL
L
L
H
V
X
V
V
X
HX
HX
HX
X
X
H
L
LH
HX
HX
H
X
X
X
HX
HX
HX
X
LLLH
X
L
HXLLLX
LLLX
HHHX
X
H
L
XVXXX
X
X
L
L
H
L
X
X
LXXX
A9 Pin High
(Other Pins OP code)
V
X
L
H
L
L
X
CA
HH
X
X
L
H
L
H
X
CA
HL
V
CKEn-1HHH
CKEnXX
L
X
L
HL
HH
HH
X
RA
L
VV
CSLH
RASLX
CASLX
WELX
X
X
DQMX
ADDR
A10/APOPcode
BANote
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation
Rev. 0.5 / June 2004 11
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HY57V561620C(L)T(P)
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)11.938(0.4700)11.735(0.4620)22.327(0.8790)22.149(0.8720)10.262(0.4040)10.058(0.3960)0.150(0.0059)0.050(0.0020)1.194(0.0470)0.991(0.0390)0.80(0.0315)BSC0.400(0.016)0.300(0.012)5deg0deg0.597(0.0235)0.406(0.0160)0.210(0.0083)0.120(0.0047)Rev. 0.5 / June 2004 12
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