Minimal instruction set computer architecture and

专利名称：Minimal instruction set computer

architecture and multiple instruction issuemethod

发明人：Michael A. Baxter申请号：US08/129697申请日：19930930公开号：US05481743A公开日：19960102

摘要：A minimal instruction set computer architecture (hyperscalar computerarchitecture) comprises a central memory, an instruction buffer, a control unit, an I/Ocontrol unit, a plurality of functional units, a plurality of register files, and a data router.In the hyperscalar computer architecture, the central memory transfers a plurality ofinstructions to the instruction buffer. The control unit receives multiple instructions fromthe instruction buffer, and automatically determines and issues the largest subset ofinstructions from those received that can be simultaneously issued to the plurality offunctional units. Each functional unit receives data from and returns computationalresults to a corresponding register file. The data router serves to transfer data betweeneach register file and any other register file, the central memory, the control unit, or theI/O control unit. The present invention also includes a multiple instruction issue methodfor issuing instructions to the hyperscalar computer architecture. The multiple instructionissue method comprises the steps of: determining a set of first source register files usedby a plurality of instructions; determining a set of second source register files used bythe plurality of instructions; determining a set of destination register files used by the

plurality of instructions; determining a largest subset of instructions within the pluralityof instructions that can be executed without a register file conflict; and issuing in paralleleach instruction within the largest subset to the plurality of functional units.

申请人：APPLE COMPUTER, INC.

代理人：Greg T. Sueoka

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