您的当前位置:首页正文

SA568A资料

2021-04-14 来源:易榕旅网
元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification150MHz phase-locked loopNE/SA568ADESCRIPTIONPIN CONFIGURATIONThe NE568A is a monolithic phase-locked loop (PLL) whichoperates from 1Hz to frequencies in excess of 150MHz and featuresD, N Packagesan extended supply voltage range and a lower temperaturecoefficient of the VVCC2120LF1CO center frequency in comparison with itspredecessor, the NE 568. The NE568A is function andGND2219LF2pin-compatible with the NE568, requiring only minor changes inGND1318LF3peripheral circuitry (see Figure 3). Temperature compensationTCAP1417LF4network is different, no resistor on Pin 12, needs to be grounded andPin 13 has a 3.9kΩ resistor to ground. Timing cap, C2, is differentTCAP2516FREQ ADJand for 70MHz operation with temperature compensation networkGND1615OUTFILTshould be 16pF, not 34pF as was used in the NE568. The NE568AVhas the following improvements: ESD protected; extended VCC1714VOUTCCrange from 4.5V to 5.5V; operating temperature range -55 to 125°CREFBYP813TCADJ2(see Signetics Military 568A data sheet); less layout sensitivity; andPNPBYP912TCADJ1lower TC of VCO (center frequency). The integrated circuit consistsINPBYP1011VINof a limiting amplifier, a current-controlled oscillator (ICO), a phasedetector, a level shift circuit, V/I and I/V converters, an output buffer,TOP VIEWSR01037and bias circuitry with temperature and frequency compensatingcharacteristics. The design of the NE568A is particularly well-suitedFigure 1. Pin Configurationfor demodulation of FM signals with extremely large deviation in•Series or shunt loop filter component capabilitysystems which require a highly linear output. In satellite receiverapplications with a 70MHz IF, the NE568A will demodulate ±20%•External loop gain controldeviations with less than 1.0% typical non-linearity. In addition to•Temperature compensatedhigh linearity, the circuit has a loop filter which can be configuredwith series or shunt elements to optimize loop dynamic•ESD protected1performance. The NE568A is available in 20-pin dual in-line and20-pin SO (surface mounted) plastic packages.APPLICATIONS•Satellite receiversFEATURES•Operation to 150MHz•Fiber optic video links•High linearity buffered output•VHF FSK demodulators•Clock RecoveryORDERING INFORMATIONDESCRIPTIONTEMPERATURE RANGEORDER CODEDWG #20-Pin Plastic Small Outline Large (SOL) Package0 to +70°CNE568ADSOT163-120-Pin Plastic Dual In-Line Package (DIP)0 to +70°CNE568ANSOT146-120-Pin Plastic Small Outline Large (SOL) Package-40 to +85°CSA568ADSOT163-120-Pin Plastic Dual In-Line Package (DIP)-40 to +85°CSA568ANSOT146-1BLOCK DIAGRAMLF1LF2LF3LF4FREQ ADJOUTFILTVOUTTCADJ2TCADJ1VIN20191817161514131211LEVEL SHIFTOUTTCADJBIASBUFCONVERTERV/II/VLEVEL SHIFTCONVERTERPHASEDETECTORAMPNOTE:Pins 4 and 5 can tolerate1000V only, and all otherpins, greater than 2000VICOfor ESD (human bodymodel).12345678910VCC2GND2GND1TCAP1TCAP2GND1VCC1REFBYPPNPBYPINPBYPSR01038Figure 2. Block Diagram1996 Feb 11853-1558 16328元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification150MHz phase-locked loopNE/SA568AABSOLUTE MAXIMUM RATINGSSYMBOLPARAMETERRATINGUNITSVCCSupply voltage6VTJJunction temperature+150°CTSTGStorage temperature range-65 to +150°CPDMAXMaximum power dissipation400mWθJAThermal resistance80°C/WELECTRICAL CHARACTERISTICSlayout-sensitive. Evaluation of performance for correlation to theThe elctrical characteristics listed below are actual tests (unlessdata sheet should be done with the circuit and layout of Figures 3, 4,otherwise stated) performed on each device with an automatic ICand 5 with the evaluation unit soldered in place. (Do not use atester prior to shipment. Performance of the device in automatedsocket!)test set-up is not necessarily optimum. The NE568A isDC ELECTRICAL CHARACTERISTICSVCC = 5V; TA = 25°C; fO = 70MHz, Test Circuit Figure 3, fIN = -20dBm, R4 = 3.9kΩ, unless otherwise specified.LIMITSSYMBOLPARAMETERTEST CONDITIONSNE/SA568AUNITSMINTYPMAXVCCSupply voltage4.555.5VICCSupply current5470mAAC ELECTRICAL CHARACTERISTICSLIMITSSYMBOLPARAMETERTEST CONDITIONSNE/SA568AUNITSMINTYPMAXfOSCMaximum oscillator operating frequency3150MHzInput signal level502000mV–201+10dBmP-PBWDemodulated bandwidthfO/7MHzNon-linearity5Dev = ±20%, Input = -20dBm1.04.0%Lock range2Input = -20dBm±25±35% of fOCapture range2Input = -20dBm±20±30% of fOTC of fOFigure 3100ppm/°CRINInput resistance41kΩOutput impedance6ΩDemodulated VOUTDev = ±20% of fPin 14O measured at0.400.52VP-PAM rejectionVIN = -20dBm (30% AM)referred to ±20% deviation50dBCentered at 70MHz, Rf2 =ODistribution61.2kΩ, C-150+15%(C2 = 16pF, R = 20pF)4 = 3.9kΩ 2 + CSTRAYfODrift with supply4.5V to 5.5V2%/VNOTE:1.Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.2.Limits are set symmetrical to fO. Actual characteristics may have asymmetry beyond the specified limits.3.Not 100% tested, but guaranteed by design.4.Input impedance depends on package and layout capacitances. See Figures 6 and 5.5.Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (VOUT). Non-linearity isthen calculated from a straight line over the deviation range specified.6.Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied.1996 Feb 12元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification150MHz phase-locked loopNE/SA568A1VC1CC2LF1202GND2LF219R1C103GND1LF318C94TCAP1LF417RFC1C25R2TCAP2FREQADJ166C11GND1OUTFILT15C87C12VR3OUT14VCC1VOUTC3VCC813R4C5C6RFC2REFBYPTCADJ2C49PNPBYPTCADJ112C13VIN10INPBYPV11C7INR5SR01039Figure 3. Test Circuit for AC ParametersFUNCTIONAL DESCRIPTIONvoltage-controlled oscillator (VCO), because the output of the phaseThe NE568A is a high-performance phase-locked loop (PLL). Thecomparator and the loop filter is a voltage. To control the frequencycircuit consists of conventional PLL elements, with special circuitryof an integrated ICO multivibrator, the control signal must befor linearized demodulated output, and high-frequency performance.conditioned by a voltage-to-current converter. In the NE568A,The process used has NPN transistors with fT > 6GHz. The highspecial circuitry predistorts the control signal to make the change ingain and bandwidth of these transistors make careful attention tofrequency a linear function over a large control-current range.layout and bypass critical for optimum performance. Theperformance of the PLL cannot be evaluated independent of theThe free-running frequency of the oscillator depends on the value oflayout. The use of the application layout in this data sheet andthe timing capacitor connected between Pins 4 and 5. The value ofsurface-mount capacitors are highly recommended as a startingthe timing capacitor depends on internal resistive components andpoint.current sources. When R2 = 1.2kΩ and R4 = 0Ω, a very closeapproximation of the correct capacitor value is:The input to the PLL is through a limiting amplifier with a gain of 200.The input of this amplifier is differential (Pins 10 and 11). ForC*+0.0014fFOsingle-ended applications, the input must be coupled through awhereDC-blocking capacitor with low impedance at the frequency ofC*+Cinterest. The single-ended input is normally applied to Pin 11 with2)CSTRAYPin 10 AC-bypassed with a low-impedance capacitor. The inputThe temperature-compensation resistor, R4, affects the actual valueimpedance is characteristically slightly above 500Ω. Impedanceof capacitance. This equation is normalized to 70MHz. See 10 formatch is not necessary, but loading the signal source should becorrection factors.avoided. When the source is 50 or 75Ω, a DC-blocking capacitor isusually all that is needed.The loop filter determines the dynamic characteristics of the loop. Inmost PLLs, the phase detector outputs are internally connected toInput amplification is low enough to assure reasonable responsethe ICO inputs. The NE568A was designed with filter output to inputtime in the case of large signals, but high enough for good AMconnections from Pins 20 (φ DET) to 17 (ICO), and Pins 19 (φ DET)rejection. After amplification, the input signal drives one port of ato 18 (ICO) external. This allows the use of both series and shuntmultiplier-cell phase detector. The other port is driven by theloop-filter elements. The loop constratints are:current-controlled oscillator (ICO). The output of the phaseKcomparator is a voltage proportional to the phase difference of theO+0.12VńRadian(PhaseDetectorConstant)input and ICO signals. The error signal is filtered with a low-passKfilter to provide a DC-correction voltage, and this voltage isO+4.2@109RadiansV(ICOConstant)at70MHz–secconverted to a current which is applied to the ICO, shifting theThe loop filter determines the general characteristics of the loop.frequency in the direction which causes the input and ICO to have aCapacitors C90° phase relationship.9, C10, and resistor R1, control the transient output ofthe phase detector. Capacitor C9 suppresses 70MHz feedthroughThe oscillator is a current-controlled multivibrator. The currentby interaction with 100Ω load resistors internal to the phasecontrol affects the charge/discharge rate of the timing capacitor. It isdetector.common for this type of oscillator to be referred to as a1996 Feb 13元器件交易网www.cecb2b.comPhilips Semiconductors150MHz phase-locked loopC9+12p(50)(fFO)At 70MHz, the calculated value is 45pF. Empirical results with thetest and application board were improved when a 47pF capacitorwas used.The natural frequency for the loop filter is set by C10 and R1. If thecenter frequency of the loop is 70MHz and the full demodulatedbandwidth is desired, i.e., fBW = fO/7 = 10MHz, and a value for R1 ischosen, the value of C10 can be calculated.C10+12pRF1fBWAlso,C11+12p350WfBW(Hz)This capacitance determines the signal bandwidth of the outputbuffer amplifier. (For further inofrmation see Philips application noteAN1881 “The NE568A Phase Locked Loop as a Wideband VideoDemodulator”.Parts List and Layout 40MHz Application NE568ADC1100nF±10%Ceramic chip1206C2118pF±2%Ceramic chip0805C2216pF±2%Ceramic ORChipC3100nF±10%Ceramic chip1206C4100nF±10%Ceramic chip1206C56.8µF±10%Tantalum35VC6100nF±10%Ceramic chip1206C7100nF±10%Ceramic chip1206C8100nF±10%Ceramic chip1206C947pF±2%Ceramic chip0805 or 1206C10560pF±2%Ceramic chip0805 or 1206C1147pF±2%Ceramic chip0805 or 1206C12100nF±10%Ceramic chip1206C13100nF±10%Ceramic chip1206R127Ω±10%Chip CR321/4WR21.2kΩTrim potR3343Ω±10%Chip CR321/4WR443.9kΩ±10%Chip CR321/4WR5350Ω±10%Chip CR321/4WRFC1510µH±10%Surface mountRFC2510µH±10%Surface mountNOTES:1.18pF with Pin 12 ground and Pin 13 no connect (open).2.C2 + CSTRAY = 16pF for temperature-compensated configurationwith R4 = 3.9kΩ.3.For 50Ω setup. R1 = 62Ω, R3 = 75Ω for 75Ω application.4.For test configuration R4 = 0Ω (GND) and C2 = 18pF.5.0Ω chip resistors (jumpers) may be substituted with minor degra-dation of performance.1996 Feb 14Product specificationNE/SA568AParts List and Layout 70MHz Application NE568ANC1100nF±10%Ceramic chip50VC2118pF±2%Ceramic chip50VC2216pF±2%Ceramic chip0805C3100nF±10%Ceramic chip50VC4100nF±10%Ceramic chip50VC56.8µF±10%Tantalum35VC6100nF±10%Ceramic chip50VC7100nF±10%Ceramic chip50VC8100nF±10%Ceramic chip50VC947pF±2%Ceramic chip50VC10560pF±2%Ceramic chip50VC1147pF±2%Ceramic chip50VC12100nF±10%Ceramic chip50VC13100nF±10%Ceramic chip50VR127Ω±10%Ceramic chip1/4WCR32R21.2kΩTrim potR3343Ω±10%Ceramic chip1/4WCR32R443.9kΩ±10%Ceramic chip1/4WCR32R5350Ω±10%Ceramic chip1/4WCR32RFC110µH±10%Surface mountRFC210µH±10%Surface mountNOTES:1.18pF with Pin 12 ground and Pin 13 no connect (open).2.Cwith R2 + CSTRAY = 16pF for temperature-compensated configuration4 = 3.9kΩ.3.For 50Ω setup. R1 = 62Ω, R3 = 75Ω for 75Ω application.4.For test configuration R4 = 0Ω (GND) and C2 = 18pF.元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

150MHz phase-locked loopNE/SA568A

NE568AKT10/89GNDVCCVOUTVINSR01040Figure 4. N Package Layout (Not Actual Size)

1996 Feb 15

元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification150MHz phase-locked loopNE/SA568A4.03.5SLTOV3.02.50102030405060708090100110120FREQUENCY (MHz)SR01044Figure 8. Typical Output Linearity100807895FO MHz7674907270856866zH80MI64CCA62mCFO7560CI5870565465525060484655444250400.80.91.01.11.21.31.41.51.6Frequency Adjust (kΩ)SR01045Figure 9. NE568: Frequency Adjust vs FO and ICC1996 Feb 16元器件交易网www.cecb2b.comPhilips SemiconductorsProduct specification150MHz phase-locked loopNE/SA568A12.011.5C = 6.8pF11.010.510.09.59.0) 8.5 Ω k(8.0ct7.5R7.06.56.05.55.04.54.0C = 16pF3.53.0C = 150pF2.52.00102030405060708090100110120130140150160FO MHzSR01046Figure 10. NE568A: Rtc (Pin 13) vs FO; Choosing the Optimum Temperature Compensation ResistorRFC1+5V10µH1VCC2LF120VCC+C1C6C50.1µF2GND2LF21910µF0.1µFR1C1027Ω560pFGND3GND1LF318J1C94TCAP1LF41747pFC2R6(Optional. Leave it18pF1.5kΩopen if not used)5TCAP2FREQADJ16NE/SA568AR2(Output Amp Gain2kΩC11Adj -2dB)647pFGND1OUTFILT15RFC2C12J310µHC80.1µF70.1µFR343ΩVOUTVCC1VOUT14(ZO = 50Ω)*C3R40.1µF83.9kΩREFBYPTCADJ213C40.1µF9PNPBYPTCADJ112J2V10ININPBYPV11C7IN0.1µFC130.1µFR551Ω*NOTE: For 75Ω output impedance, use R3 = 68Ω.SR01113Figure 11. Phase Locked Loop NE/SA568A1996 Feb 17元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

150MHz phase-locked loopNE/SA568A

1996 Feb 18

元器件交易网www.cecb2b.com

Philips Semiconductors

Product specification

150MHz phase-locked loopNE/SA568A

1996 Feb 19

因篇幅问题不能全部显示,请点此查看更多更全内容