专利名称：Higher voltage drain extended MOS
transistors with self-aligned channel anddrain extensions
发明人：Jozef Czeslaw Mitros申请号：US09952404申请日：20010914
公开号：US20020055233A1公开日：20020509
专利附图：
摘要：An integrated circuit drain extension transistor. A transistor gate () is formedover a CMOS n-well region (). A transistor source extension region (), and drain extension
region () are formed in the CMOS well region (). A transistor region () is formed in thesource extension region and a transistor drain region is formed between two drainalignment structures (), () in the drain extension region ().
申请人：MITROS JOZEF CZESLAW
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