专利名称：Reduced parasitic capacitance and contact
resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions
发明人：Kangguo Cheng,Ramachandra Divakaruni申请号：US15072920申请日：20160317公开号：US09735173B1公开日：20170815
专利附图：
摘要：A semiconductor device includes a buried dielectric layer and a semiconductor
layer provided on the buried dielectric layer. A gate structure is formed on the
semiconductor layer and has portions of the semiconductor layer extending beyond thegate structure. Source and drain regions are wrapped around ends of the semiconductorlayer such that a first portion of the source and drain regions is formed on a first side ofthe semiconductor layer adjacent to the gate structure, and a second portion of thesource and drain regions is formed on a second side of the semiconductor layer oppositethe first side.
申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION
地址：Armonk NY US
国籍：US
代理机构：Tutunijan & Bitetto, P.C.
代理人：Vazken Alexanian
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容