White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED*
1GB – 2x64Mx64 DDR SDRAM REGISTERED w/PLL
FEATURES
Double-data-rate architecture
Clock speeds of 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power Supply:
• VCC = VCCQ = +2.5V (133 and 166MHz) JEDEC standard 184 pin DIMM package PCB height: 30.48 (1.20\") MAX
• JD3: 30.48mm (1.20\")
NOTE: Consult factory for availability of:
• RoHS compliant products • Vendor source control options • Industrial temperature option
* This product is under development, is not qualifi ed or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The W3EG264M64ETSR is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 64Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock SpeedCL-tRCD-tRP
166MHz2.5-3-3
DDR266 @CL=2
133MHz2-3-3
DDR266 @CL=2.5
133MHz2.5-3-3
April 2005Rev. 0
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White Electronic DesignsPIN CONFIGURATION
PIN12345678910111213141516171819202122232425262728293031323334353637383940414243444546
SYMBOLVREFDQ0VSSDQ1DQS0DQ2VCCDQ3NCRESET#VSSDQ8DQ9DQS1VCCQNCNCVSSDQ10DQ11CKE0VCCQDQ16DQ17DQS2VSSA9DQ18A7VCCQDQ19A5DQ24VSSDQ25DQS3A4VCCDQ26DQ27A2VSSA1NCNCVCC
PIN47484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192
SYMBOLNCA0NCVSSNCBA1DQ32VCCQDQ33DQS4DQ34VSSBA0DQ35DQ40VCCQWE#DQ41CAS#VSSDQS5DQ42DQ43VCCNCDQ48DQ49VSSNCNCVCCQDQS6DQ50DQ51VSSVCCIDDQ56DQ57VCCDQS7DQ58DQ59VSSNCSDASCL
PIN93949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138
SYMBOLVSSDQ4DQ5VCCQDQM0DQ6DQ7VSSNCNCNCVCCQDQ12DQ13DQM1VCCDQ14DQ15CKE1VCCQNCDQ20A12VSSDQ21A11DQM2VCCDQ22A8DQ23VSSA6DQ28DQ29VCCQDQM3A3DQ30VSSDQ31NCNCVCCQCK0CK0#
PIN139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
SYMBOLVSSNCA10NCVCCQNCVSSDQ36DQ37VCCDQM4DQ38DQ39VSSDQ44RAS#DQ45VCCQCS0#CS1#DQM5VSSDQ46DQ47NCVCCQDQ52DQ53A13VCCDQM6DQ54DQ55VCCQNCDQ60DQ61VSSDQM7DQ62DQ63VCCQSA0SA1SA2VCCSPD
W3EG264M64ETSR-JD3
ADVANCED
PIN NAMES
A0-A13BA0-BA1DQ0-DQ63DQS0-DQS7CK0, CK0#CKE0, CKE1CS0#, CS1#RAS#CAS#
DQM0-DQM7WE#VCCVCCQVSSVREFVCCSPDSDASCLSA0-SA2VCCIDNC
RESET#
Address input (Multiplexed)Bank Select AddressData Input/Output
Data Strobe Input/OutputClock Input
Clock Enable inputChip Select InputRow Address StrobeColumn Address StrobeData-in MaskWrite Enable
Power Supply (2.5V)
Power Supply for DQS (2.5V)Ground
Power Supply for ReferenceSerial EEPROM Power Supply (2.3V to 3.6V)Serial data I/OSerial clock
Address in EEPROMVCC Indentifi cation FlagNo ConnectReset Enable
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
RCS1#DQS4DQM4DQMDQ DQDQDQDQDQDQDQCS#DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSDQS0DQM0DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7RCS0#DQMCS#DQSDQDQ DQ DQ DQ DQ DQ DQ DQS1DQM1DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSDQS5DQM5DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSDQS2DQM2DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSDQS6DQM6DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSDQS3DQM3DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSDQS7DQM7DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63DQMCS#DQSDQ DQ DQ DQ DQ DQ DQ DQ DQMDQ DQDQDQDQDQDQDQCS#DQSCS0#CS1#BA0-BA1A0-A13RAS#CAS#CKE0CKE1WE#PCKPCK#R E G IS T E R RCS0#RCS1#RBA0-RBA1 RA0-RA13 RRAS#RCAS#RCKE0RCKE1RWE#RESET#120BA0-BA1: SDRAMs A0-A13: SDRAMsRAS#: SDRAMsCAS#: SDRAMsCKE: SDRAMsCKE: SDRAMsWE#: DQRAMsSCLWPCK0CK0#PLLDDR SDRAMsREGISTER x 1SERIAL PDA0A1A2SDASA0SA1SA2VCCSPDVCCQVCCVREFVSSNote: All resistor values are 22Ω unless otherwise indicated.SPDDDR SDRAMSDDR SDRAMSDDR SDRAMSDDR SDRAMSApril 2005Rev. 0
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White Electronic DesignsParameter
Voltage on any pin relative to VSSVoltage on VCC supply relative to VSSStorage TemperaturePower DissipationShort Circuit Current
Note:
W3EG264M64ETSR-JD3
ADVANCED
ABSOLUTE MAXIMUM RATINGS
SymbolVIN, VOUTVCC, VCCQTSTGPDIOS
Value-0.5 to 3.6-1.0 to 3.6-55 to +150
1850
UnitsVV°C WmA
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
ParameterSupply VoltageSupply VoltageReference VoltageTermination VoltageInput High VoltageInput Low VoltageOutput High VoltageOutput Low Voltage
SymbolVCCVCCQVREFVTTVIHVILVOHVOL
Min2.32.31.151.15VREF + 0.15-0.3VTT + 0.76—
Max2.72.71.351.35VCCQ + 0.3VREF -0.15—VTT-0.76
UnitVVVVVVVV
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (A0-A13)Input Capacitance (RAS#,CAS#,WE#)Input Capacitance (CKE0)Input Capacitance (CK0#,CK0)Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM3, DQM5-DQM8)Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
SymbolCIN1CIN2CIN3CIN4CIN5CIN6CIN7COUT
Max6.56.56.55.56.5136.513
UnitpFpFpFpFpFpFpFpF
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
ParameterOperating Current
DDR333@ CL=2.5Max1840
DDR266@ CL=2Max1840
DDR266@ CL=2.5Max1840
SymbolIDD0
Conditions
One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control inputs changing once every two cycles.One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.
All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.
One device bank active; Power-Down mode; tCK (MIN); CKE=(low)
CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle.tRC = tRC (MIN)CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.
UnitsmA
Operating CurrentIDD1208020802080mA
Precharge Power-Down Standby CurrentIdle Standby Current
IDD2PIDD2F
80720
80720
80720
rnAmA
Active Power-Down Standby Current Active Standby Current
IDD3P IDD3N
560800
560800
560800
mAmA
Operating CurrentIDD4R212021202120mA
Operating CurrentIDD4W220022002200rnA
Auto Refresh CurrentSelf Refresh CurrentOperating Current
IDD5IDD6IDD7A
3120804040
3120804040
3120804040
mAmAmA
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
ParameterOperating Current
DDR333@ CL=2.5Max2480
DDR266@ CL=2Max2480
DDR266@ CL=2.5Max2480
SymbolIDD0
Conditions
One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control inputs changing once every two cycles.One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.
All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.
One device bank active; Power-Down mode; tCK (MIN); CKE=(low)
CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle.tRC = tRC (MIN)CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.
UnitsmA
Operating CurrentIDD1272027202720mA
Precharge Power-Down Standby CurrentIdle Standby Current
IDD2PIDD2F
801030
801030
801030
rnAmA
Active Power-Down Standby Current Active Standby Current
IDD3P IDD3N
5601110
5601110
5601110
mAmA
Operating CurrentIDD4R276027602760mA
Operating CurrentIDD4W284028402840rnA
Auto Refresh CurrentSelf Refresh CurrentOperating Current
IDD5IDD6IDD7A
37404104680
37404104680
37404104680
mAmAmA
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC CharacteristicsParameter
Access window of DQs from CK, CK#CK high-level widthCK low-level widthClock cycle time
DQ and DM input hold time relative to DQSDQ and DM input setup time relative to DQSDQ and DM input pulse width (for each input)Access window of DQS from CK, CK#DQS input high pulse widthDQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per accessWrite command to fi rst DQS latching transitionDQS falling edge to CK rising - setup timeDQS falling edge from CK rising - hold timeHalf clock period
Data-out high-impedance window from CK, CK#Data-out low-impedance window from CK, CK#Address and control input hold time (fast slew rate)Address and control input set-up time (fast slew rate)Address and control input hold time (slow slew rate)Address and control input setup time (slow slew rate)Address and control input pulse width (for each input)LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to fi rst DQ to go non-valid, per accessData hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge commandACTIVE to ACTIVE/AUTO REFRESH command periodAUTO REFRESH command period
CL=2.5CL=2
SymboltACtCHtCLtCK (2.5)tCK (2)tDHtDStDIPWtDQSCKtDQSHtDQSLtDQSQtDQSStDSStDSHtHPtHZtLZtIHftISftIHstISstIPWtMRDtQHtQHStRAStRAPtRCtRFC
42156072-0.70.750.750.80.82.212tHP - tQHS
0.5572,000
40156075
tCH, tCL
0.7
-0.750.900.90112.215tHP - tQHS
0.75120,0000.75Min-0.70.450.4567.50.450.451.75-0.60.350.35
0.451.250.20.2
tCH, tCL
0.75
0.75
+0.6335
Max+0.70.550.551313
Min-0.750.450.457.57.50.50.51.75-0.750.350.35
0.351.250.20.2+0.75263/265
Max+0.750.550.551313
UnitsnstCKtCKnsnsnsnsnsnstCKtCKnstCKtCKtCKnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
211513, 14188, 198, 20666613, 141616222214, 1714, 1717Notes
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC CharacteristicsParameter
ACTIVE to READ or WRITE delayPRECHARGE command periodDQS read preambleDQS read postamble
ACTIVE bank a to ACTIVE bank b commandDQS write preamble
DQS write preamble setup timeDQS write postambleWrite recovery time
Internal WRITE to READ command delayData valid output window
REFRESH to REFRESH command intervalAverage periodic refresh intervalTerminating voltage delay to VCC
Exit SELF REFRESH to non-READ commandExit SELF REFRESH to READ command
SymboltRCDtRPtRPREtRPSTtRRDtWPREtWPREStWPSTtWRtWTRNAtREFCtREFItVTDtXSNRtXSRD
075200Min15150.90.4120.2500.4151tQH - tDQSQ
70.37.8
075200
0.61.10.6335
Max
Min15150.90.4150.2500.4151tQH - tDQSQ
70.37.80.61.10.6
263/265
Max
UnitsnsnstCKtCKnstCKnstCKnstCKnsμsμsnsnstCK
1310, 11919Notes
April 2005Rev. 0
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White Electronic DesignsNotes
1. 2.
All voltages referenced to VSS
Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifi cations and device operations are guaranteed for the full voltage range specifi ed.Outputs are measured with equivalent load:
W3EG264M64ETSR-JD3
ADVANCED
3.
12. The refresh period is 64ms. This equates to an average refresh
rate of 15.625µs (256Mb component) or 7.8125µs (512 Mb component). However, an AUTO REFRESH command must be asserted at least once every 140.6µs (256 Mb component) or 70.3µs (512Mb component); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.13. The valid data window is derived by achieving other specifi cations
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.14. Referenced to each output group: x8 = DQS with DQ0-DQ8.
VTTOutput(VOUT)50ΩReference Point30pF4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).The AC and DC input level specifi cations are defi ned in the SSTL_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level).
Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfi ed prior to the internal precharge command being issued.16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns (2V/ns differentially).17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain.18. tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.19. This maximum value is derived from the referenced test load. In
practice, the values obtained in a typical terminated design may refl ect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition.20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).
5.
6.
7.
8. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ).9.
The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus turnaround.11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS.
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
1. Typical Case : VCC=2.5V, T=25°C2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA4. Timing Patterns :
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCKRead : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address
changing; 50% of data changing at every burstDDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address
changing; 50% of data changing at every burst
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C2. Worst Case : VCC=2.7V, T=10°C
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA4. Timing Patterns :
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCKRead with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
•
•
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOPA (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
PART NUMBERING GUIDE
W 3 E G 264M 64 E T S R xxx JD3 x GWEDCMEMORY
DDRGOLD
DEPTH (Dual Rank)
BUS WIDTH
x8TSOP2.5V
REGISTEREDSPEED (MHz)PACKAGE
COMPONENT VENDOR
NAME
(M = MICRON)(S = SAMSUNG)
RoHS COMPLIANT
April 2005Rev. 0
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White Electronic DesignsW3EG264M64ETSR-JD3
ADVANCED
ORDERING INFORMATION FOR JD3
Part Number
W3EG264M64ETSR335JD3xGW3EG264M64ETSR263JD3xGW3EG264M64ETSR265JD3xG
Speed166MHz/333Mb/s133MHz/266Mb/s133MHz/266Mb/s
CAS Latency
2.522.5
tRCD333
tRP333
Height*30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")
NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • V endor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))3.99(0.157)(MIN)3.81(0.150 MAX)17.78(0.700)10.01(0.394)6.35(0.250)64.77(2.550)1.27(0.050 TYP.)30.48(1.20 MAX)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
April 2005Rev. 0
12White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
元器件交易网www.cecb2b.com
White Electronic DesignsDocument Title
1GB – 2x64Mx64 DDR SDRAM REGISTERED w/PLL
W3EG264M64ETSR-JD3
ADVANCED
Revision HistoryRev #
Rev 0
History
Created
Release Date
4-05
Status
Advanced
April 2005Rev. 0
13White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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