ADC121S101_06资料

ADC121S101SingleChannel,0.5to1Msps,12-BitA/DConverterApril2006

ADC121S101

SingleChannel,0.5to1Msps,12-BitA/DConverter

GeneralDescription

TheADC121S101isalow-power,singlechannelCMOS12-bitanalog-to-digitalconverterwithahigh-speedserialinterface.Unliketheconventionalpracticeofspecifyingper-formanceatasinglesamplerateonly,theADC121S101isfullyspecifiedoverasampleraterangeof500kspsto1Msps.Theconverterisbaseduponasuccessive-approximationregisterarchitecturewithaninternaltrack-and-holdcircuit.

Theoutputserialdataisstraightbinary,andiscompatiblewithseveralstandards,suchasSPI™,QSPI™,MICROWIRE,andmanycommonDSPserialinterfaces.TheADC121S101operateswithasinglesupplythatcanrangefrom+2.7Vto+5.25V.Normalpowerconsumptionusinga+3Vor+5Vsupplyis2.0mWand10mW,respec-tively.Thepower-downfeaturereducesthepowerconsump-tiontoaslowas2.6µWusinga+5Vsupply.

TheADC121S101ispackagedin6-leadLLPandSOT-23packages.Operationovertheindustrialtemperaturerangeof−40˚Cto+125˚Cisguaranteed.

Features

nnnnn

Specifiedoverarangeofsamplerates.6-leadLLPandSOT-23packagesVariablepowermanagement

Singlepowersupplywith2.7V-5.25VrangeSPI™/QSPI™/MICROWIRE/DSPcompatible

KeySpecifications

nnnn

DNLINLSNR

PowerConsumption—3VSupply—5VSupply

+0.5/−0.3LSB(typ)

±0.40LSB(typ)72.5dB(typ)

2.0mW(typ)10mW(typ)

Applications

nPortableSystems

nRemoteDataAcquisition

nInstrumentationandControlSystems

Pin-CompatibleAlternativesbyResolutionandSpeed

Alldevicesarefullypinandfunctioncompatible.

Resolution

50to200ksps

12-bit10-bit8-bit

ADC121S021ADC101S021ADC081S021

SpecifiedforSampleRateRangeof:

200to500kspsADC121S051ADC101S051ADC081S051

500kspsto1Msps

ADC121S101ADC101S101ADC081S101

ConnectionDiagram

20145005

OrderingInformation

OrderCodeADC121S101CISDADC121S101CISDXADC121S101CIMFADC121S101CIMFADC121S101EVAL

TRI-STATE®isatrademarkofNationalSemiconductorCorporationQSPI™andSPI™aretrademarksofMotorola,Inc.

TemperatureRange−40˚Cto+125˚C−40˚Cto+125˚C−40˚Cto+125˚C−40˚Cto+125˚C

Description6-LeadLLPPackage

6-LeadLLPPackage,Tape&Reel

6-LeadSOT-23Package

6-LeadSOT-23Package,Tape&Reel

EvaluationBoard

TopMarkX1CX1CX01CX01C

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ADC121S101BlockDiagram

20145007

PinDescriptionsandEquivalentCircuits

PinNo.ANALOGI/O

3DIGITALI/O

456

POWERSUPPLY

12PAD

VAGNDGND

Positivesupplypin.Thispinshouldbeconnectedtoaquiet+2.7Vto+5.25VsourceandbypassedtoGNDwitha1µFcapacitoranda0.1µFmonolithiccapacitorlocatedwithin1cmofthepowerpin.

Thegroundreturnforthesupplyandsignals.

ForpackagesuffixCISD(X)only,itisrecommendedthatthecenterpadshouldbeconnectedtoground.

SCLKSDATACS

Digitalclockinput.Thisclockdirectlycontrolstheconversionandreadoutprocesses.Digitaldataoutput.TheoutputsamplesareclockedoutofthispinonfallingedgesoftheSCLKpin.

Chipselect.OnthefallingedgeofCS,aconversionprocessbegins.

VINAnaloginput.Thissignalcanrangefrom0VtoVA.

Symbol

Description

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ADC121S101AbsoluteMaximumRatings(Notes1,2)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.AnalogSupplyVoltageVAVoltageonAnyDigitalPintoGNDVoltageonAnyAnalogPintoGNDInputCurrentatAnyPin(Note3)PackageInputCurrent(Note3)PowerConsumptionatTA=25˚CESDSusceptibility(Note5)HumanBodyModelMachineModelJunctionTemperatureStorageTemperature

−0.3Vto6.5V−0.3Vto6.5V−0.3Vto(VA+0.3V)

OperatingRatings(Notes1,2)

OperatingTemperatureRangeVASupplyVoltage

DigitalInputPinsVoltageRange(regardlessofsupplyvoltage)AnalogInputPinsVoltageRangeClockFrequencySampleRate

−40˚C≤TA≤+125˚C

+2.7Vto+5.25V−0.3Vto5.25V

0VtoVA1MHzto20MHz

upto1Msps

±10mA±20mA

See(Note4)

3500V300V+150˚C

−65˚Cto+150˚C

PackageThermalResistance

Package6-leadLLP6-leadSOT-23

θJA94˚C/W265˚C/W

SolderingprocessmustcomplywithNationalSemiconduc-tor’sReflowTemperatureProfilespecifications.Refertowww.national.com/packaging.(Note6)

ADC121S101ConverterElectricalCharacteristics(Notes7,9)

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,fSCLK=10MHzto20MHz,CL=15pF,

fSAMPLE=500kspsto1Msps,unlessotherwisenoted.BoldfacelimitsapplyforTA=-40˚Cto+85˚C:allotherlimitsTA=25˚Cunlessotherwisenoted.Symbol

Parameter

Conditions

Typical

Limits(Note9)

Units

STATICCONVERTERCHARACTERISTICS

ResolutionwithNoMissingCodes

VA=+2.7vto+3.6V−40˚C≤TA≤125˚C−40˚C≤TA≤+85˚CVA=+2.7Vto+3.6V

INL

IntegralNon-Linearity

TA=125˚C

VA=+2.7vto+3.6V−40˚C≤TA≤+85˚CVA=+2.7Vto+3.6VTA=125˚C

VA=+2.7vto+3.6V−40˚C≤TA≤125˚CVA=+2.7vto+3.6V−40˚C≤TA≤125˚CVA=+2.7to+3.6V

SOT-23LLPSOT-23LLP

+0.5−0.3

SOT-23LLP

+0.4-0.4+0.4-0.4

12

BitsLSB(max)LSB(min)LSB(max)LSB(min)LSB(max)LSB(min)LSB(max)LSB(min)LSB(max)LSB(min)LSB(max)LSB(max)LSB(min)LSB(max)LSB(max)

±1.0

+1.0-1.2+1.0-1.1+1.0-1.3+1.0-0.9

DNLDifferentialNon-Linearity

±1.0

±0.1±0.20±0.20

±1.2±1.2±1.5

VOFFGE

OffsetErrorGainError

DYNAMICCONVERTERCHARACTERISTICSSINAD

VA=+2.7to5.25V

Signal-to-NoisePlusDistortionRatio−40˚C≤TA≤125˚C

fIN=100kHz,−0.02dBFS

VA=+2.7to5.25V−40˚C≤TA≤+85˚C

fIN=100kHz,−0.02dBFSVA=+2.7to5.25VTA=+125˚C

fIN=100kHz,−0.02dBFS

72

70

dB(min)

72.570.8

dB(min)

70.6

SNRSignal-to-NoiseRatio

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ADC121S101ADC121S101ConverterElectricalCharacteristics(Notes7,9)

(Continued)

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,fSCLK=10MHzto20MHz,CL=15pF,

fSAMPLE=500kspsto1Msps,unlessotherwisenoted.BoldfacelimitsapplyforTA=-40˚Cto+85˚C:allotherlimitsTA=25˚Cunlessotherwisenoted.

Parameter

Conditions

Typical

Limits(Note9)

Units

Symbol

DYNAMICCONVERTERCHARACTERISTICSTHDSFDRENOB

TotalHarmonicDistortionSpurious-FreeDynamicRangeEffectiveNumberofBits

IntermodulationDistortion,SecondOrderTerms

IntermodulationDistortion,ThirdOrderTerms

-3dBFullPowerBandwidth

VA=+2.7to5.25V

fIN=100kHz,−0.02dBFSVA=+2.7to5.25V

fIN=100kHz,−0.02dBFSVA=+2.7to5.25V

fIN=100kHz,−0.02dBFSVA=+5.25V

fa=103.5kHz,fb=113.5kHzVA=+5.25V

fa=103.5kHz,fb=113.5kHzVA=+5VVA=+3V

−808211.6−78−781180toVA11.3

dB(max)dB(min)Bits(min)

dBdBMHzMHzV

IMD

FPBW

ANALOGINPUTCHARACTERISTICSVINIDCLCINAInputRangeDCLeakageCurrentInputCapacitance

TrackModeHoldModeVA=+5.25VVA=+3.6VVA=+5VVA=+3VVIN=0VorVA304

2.42.10.80.4

±1

µA(max)pFpFV(min)V(min)V(max)V(max)µA(max)pF(max)V(min)VV(max)V

DIGITALINPUTCHARACTERISTICSVIHVILIINCINDInputHighVoltageInputLowVoltageInputCurrent

DigitalInputCapacitance

ISOURCE=200µAISOURCE=1mAISINK=200µAISINK=1mA

±0.1

2VA−0.07VA−0.10.030.1

±1

4VA−0.20.4

DIGITALOUTPUTCHARACTERISTICSVOHVOLIOZH,IOZLCOUTOutputHighVoltageOutputLowVoltage

TRI-STATE®LeakageCurrentTRI-STATE®OutputCapacitanceOutputCoding

POWERSUPPLYCHARACTERISTICSVASupplyVoltage

VA=+5.25V,

fSAMPLE=1MspsVA=+3.6V,

fSAMPLE=1MspsfSCLK=0MHz,VA=+5V,fSAMPLE=0ksps

fSCLK=20MHz,VA=+5V,fSAMPLE=0ksps

2.00.650060

2.75.253.21.5

V(min)V(max)mA(max)mA(max)

nAµA

±0.1

2

±10

4

µA(max)pF(max)

Straight(Natural)Binary

SupplyCurrent,NormalMode(Operational,CSlow)

IASupplyCurrent,Shutdown(CShigh)

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ADC121S101ADC121S101ConverterElectricalCharacteristics(Notes7,9)

(Continued)

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,fSCLK=10MHzto20MHz,CL=15pF,

fSAMPLE=500kspsto1Msps,unlessotherwisenoted.BoldfacelimitsapplyforTA=-40˚Cto+85˚C:allotherlimitsTA=25˚Cunlessotherwisenoted.

Parameter

Conditions

Typical

Limits(Note9)164.5

Units

Symbol

POWERSUPPLYCHARACTERISTICS

PowerConsumption,NormalMode(Operational,CSlow)

PDPowerConsumption,Shutdown(CShigh)

VA=+5VVA=+3V

fSCLK=0MHz,VA=+5VfSAMPLE=0ksps

fSCLK=20MHz,VA=+5V,fSAMPLE=0ksps

102.02.5300

mW(max)mW(max)

µWµW

ACELECTRICALCHARACTERISTICSfSCLKfStCONVDCtACQtQUIETtADtAJClockFrequencySampleRateConversionTimeSCLKDutyCycle

Track/HoldAcquisitionTimeThroughputTime(Note10)ApertureDelayApertureJitter

330

AcquisitionTime+ConversionTimefSCLK=20MHz

50

(Note8)(Note8)

102050011640604002050

MHz(min)MHz(max)ksps(min)Msps(max)SCLKcycles%(min)%(max)ns(max)SCLKcyclesns(min)nsps

ADC121S101TimingSpecifications

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,fSCLK=10.0MHzto20.0MHz,CL=25pF,fSAMPLE=500kspsto1Msps,BoldfacelimitsapplyforTA=-40˚Cto+85˚C;allotherlimitsTA=25˚C.SymboltCStSUtENtACCtCLtCHtHParameter

MinimumCSPulseWidthCStoSCLKSetupTime

DelayfromCSUntilSDATATRI-STATE®Disabled(Note11)

DataAccessTimeafterSCLKFallingEdge(Note12)

SCLKLowPulseWidthSCLKHighPulseWidthSCLKtoDataValidHoldTime

VA=+2.7Vto+3.6VVA=+4.75Vto+5.25VVA=+2.7Vto+3.6VVA=+4.75Vto+5.25V

1

VA=+2.7to+3.6VA=+4.75to+5.25

Conditions

Typical

Limits10102040200.4xtSCLK0.4xtSCLK75256255

Unitsns(min)ns(min)ns(max)ns(max)ns(max)ns(min)ns(min)ns(min)ns(min)ns(max)ns(min)ns(max)ns(min)µs

tDISSCLKFallingEdgetoSDATAHighImpedance(Note13)

Power-UpTimefromFullPower-Down

tPOWER-UPNote1:AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotguaranteespecificperformancelimits.Forguaranteedspecificationsandtestconditions,seetheElectricalCharacteristics.Theguaranteedspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.

Note2:AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.

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ADC121S101ADC121S101TimingSpecifications

(Continued)

Note3:Whentheinputvoltageatanypinexceedsthepowersupply(thatis,VINVA),thecurrentatthatpinshouldbelimitedto10mA.The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof10mAtotwo.TheAbsoluteMaximumRatingspecificationdoesnotapplytotheVApin.ThecurrentintotheVApinislimitedbytheAnalogSupplyVoltagespecification.

Note4:Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150˚C.ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDmax=(TJmax−TA)/θJA.Thevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.g.wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).Obviously,suchconditionsshouldalwaysbeavoided.

Note5:Humanbodymodelis100pFcapacitordischargedthrougha1.5kΩresistor.Machinemodelis220pFdischargedthroughzeroohms.Note6:Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.Note7:TestedlimitsareguaranteedtoNational’sAOQL(AverageOutgoingQualityLevel).

Note8:Thisisthefrequencyrangeoverwhichtheelectricalperformanceisguaranteed.ThedeviceisfunctionaloverawiderrangewhichisspecifiedunderOperatingRatings.

Note9:Datasheetmin/maxspecificationlimitsareguaranteedbydesign,test,orstatisticalanalysis.Note10:MinimumQuietTimerequiredbybusrelinquishandthestartofthenextconversion.

Note11:MeasuredwiththetimingtestcircuitshowninFigure1anddefinedasthetimetakenbytheoutputsignaltocross1.0V.Note12:MeasuredwiththetimingtestcircuitshowninFigure1anddefinedasthetimetakenbytheoutputsignaltocross1.0Vor2.0V.

Note13:tDISisderivedfromthetimetakenbytheoutputstochangeby0.5VwiththetimingtestcircuitshowninFigure1.Themeasurednumberisthenadjustedtoremovetheeffectsofchargingordischargingtheoutputcapacitance.ThismeansthattDISisthetruebusrelinquishtime,independentofthebusloading.

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ADC121S101TimingDiagrams

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FIGURE1.TimingTestCircuit

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FIGURE2.ADC121S101SerialTimingDiagram

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ADC121S101SpecificationDefinitions

ACQUISITIONTIMEisthetimerequiredtoacquiretheinputvoltage.Thatis,itistimerequiredfortheholdcapacitortochargeuptotheinputvoltage.

APERTUREDELAYisthetimebetweenthefourthfallingSCLKedgeofaconversionandthetimewhentheinputsignalisacquiredorheldforconversion.

APERTUREJITTER(APERTUREUNCERTAINTY)isthevariationinaperturedelayfromsampletosample.Aperturejittermanifestsitselfasnoiseintheoutput.

CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword.

DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.Thespeci-ficationherereferstotheSCLK.

EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.ENOBisdefinedas(SINAD−1.76)/6.02andsaysthattheconverterisequiva-lenttoaperfectADCofthis(ENOB)numberofbits.FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.

GAINERRORisthedeviationofthelastcodetransition(111...110)to(111...111)fromtheideal(VREF−1.5LSB),afteradjustingforoffseterror.

INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(1⁄2LSBbelowthefirstcodetransition)throughpositivefullscale(1⁄2LSBabovethelastcodetransition).Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue.

INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalspectralcomponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.Itisdefinedastheratioofthepowerinthesecondandthird

orderintermodulationproductstothesumofthepowerinbothoftheoriginalfrequencies.IMDisusuallyexpressedindB.

MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.TheADC121S101isguaranteednottohaveanymissingcodes.

OFFSETERRORisthedeviationofthefirstcodetransition(000...000)to(000...001)fromtheideal(i.e.GND+0.5LSB).

SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingharmonicsord.c.

SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherspectralcompo-nentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.c.

SPURIOUSFREEDYNAMICRANGE(SFDR)isthediffer-ence,expressedindB,betweenthedesiredsignalampli-tudetotheamplitudeofthepeakspuriousspectralcompo-nent,whereaspuriousspectralcomponentisanysignalpresentintheoutputspectrumthatisnotpresentattheinputandmayormaynotbeaharmonic.

TOTALHARMONICDISTORTION(THD)istheratio,ex-pressedindBordBc,ofthermstotalofthefirstfiveharmoniccomponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.THDiscalcu-latedas

whereAf1istheRMSpoweroftheinputfrequencyattheoutputandAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies.

THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwosuccessiveconversion.Itistheacquisitiontimeplustheconversiontime.

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ADC121S101TypicalPerformanceCharacteristics

fSCLK=10MHzto20MHz,fINDNL

fSCLK=10MHz

TA=+25˚C,fSAMPLE=500kspsto1Msps,

=100kHzunlessotherwisestated.

fSCLKINL

=10MHz

2014502020145021

DNL

fSCLK=20MHzINL

fSCLK=20MHz

2014506020145061

DNLvs.ClockFrequencyINLvs.ClockFrequency

2014506520145066

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ADC121S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kspsto1Msps,

fSCLK=10MHzto20MHz,fIN=100kHzunlessotherwisestated.(Continued)

SNRvs.ClockFrequency

SINADvs.ClockFrequency

2014506320145064

SFDRvs.ClockFrequencyTHDvs.ClockFrequency

2014506720145068

SpectralResponse,VA=5.25V

fSCLK=10MHzSpectralResponse,VA=5.25V

fSCLK=20MHz

2014506920145070

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ADC121S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kspsto1Msps,

fSCLK=10MHzto20MHz,fIN=100kHzunlessotherwisestated.(Continued)

PowerConsumptionvs.Throughput,

fSCLK=20MHz

20145055

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ADC121S101ApplicationsInformation

1.0ADC121S101OPERATION

TheADC121S101isasuccessive-approximationanalog-to-digitalconverterdesignedaroundacharge-redistributiondigital-to-analogconvertercore.SimplifiedschematicsoftheADC121S101inbothtrackandholdmodesareshowninFigure3andFigure4,respectively.InFigure3,thedeviceisintrackmode:switchSW1connectsthesamplingcapacitortotheinput,andSW2balancesthecomparatorinputs.ThedeviceisinthisstateuntilCSisbroughtlow,atwhichpointthedevicemovestoholdmode.

Figure4showsthedeviceinholdmode:switchSW1con-nectsthesamplingcapacitortoground,maintainingthesampledvoltage,andswitchSW2unbalancesthecompara-tor.Thecontrollogictheninstructsthecharge-redistributionDACtoaddorsubtractfixedamountsofchargefromthesamplingcapacitoruntilthecomparatorisbalanced.Whenthecomparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.Thedevicemovesfromholdmodetotrackmodeonthe13thrisingedgeofSCLK.

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FIGURE3.ADC121S101inTrackMode

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FIGURE4.ADC121S101inHoldMode

2.0USINGTHEADC121S101

TheserialinterfacetimingdiagramfortheADC121S101isshowninFigure2.CSischipselect,whichinitiatesconver-sionsontheADC121S101andframestheserialdatatrans-fers.SCLK(serialclock)controlsboththeconversionpro-cessandthetimingofserialdata.SDATAistheserialdataoutpin,whereaconversionresultisfoundasaserialdatastream.

BasicoperationoftheADC121S101beginswithCSgoinglow,whichinitiatesaconversionprocessanddatatransfer.SubsequentrisingandfallingedgesofSCLKwillbelabelledwithreferencetothefallingedgeofCS;forexample,\"thethirdfallingedgeofSCLK\"shallrefertothethirdfallingedgeofSCLKafterCSgoeslow.

AtthefallofCS,theSDATApincomesoutofTRI-STATE,andtheconvertermovesfromtrackmodetoholdmode.Theinputsignalissampledandheldforconversiononthefalling

edgeofCS.Theconvertermovesfromholdmodetotrackmodeonthe13thrisingedgeofSCLK(seeFigure2).TheSDATApinwillbeplacedbackintoTRI-STATEafterthe16thfallingedgeofSCLK,orattherisingedgeofCS,whicheveroccursfirst.Afteraconversioniscompleted,thequiettimetQUIETmustbesatisfiedbeforebringingCSlowagaintobeginanotherconversion.

SixteenSCLKcyclesarerequiredtoreadacompletesamplefromtheADC121S101.Thesamplebits(includingleadingzeroes)areclockedoutonfallingedgesofSCLK,andareintendedtobeclockedinbyareceiveronsubse-quentfallingedgesofSCLK.TheADC121S101willproducethreeleadingzerobitsonSDATA,followedbytwelvedatabits,mostsignificantfirst.

IfCSgoeslowbeforetherisingedgeofSCLK,anadditional(fourth)zerobitmaybecapturedbythenextfallingedgeofSCLK.

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ADC121S101ApplicationsInformation

3.0ADC121S101TRANSFERFUNCTION

(Continued)

5.0ANALOGINPUTS

AnequivalentcircuitfortheADC121S101’sinputisshowninFigure7.DiodesD1andD2provideESDprotectionfortheanaloginputs.Atnotimeshouldtheanaloginputgobeyond(VA+300mV)or(GND−300mV),astheseESDdiodeswillbeginconducting,whichcouldresultinerraticoperation.ThecapacitorC1inFigure7hasatypicalvalueof4pF,andismainlythepackagepincapacitance.ResistorR1istheonresistanceofthetrack/holdswitch,andistypically500ohms.CapacitorC2istheADC121S101samplingcapacitorandistypically26pF.TheADC121S101willdeliverbestperformancewhendrivenbyalow-impedancesourcetoeliminatedistortioncausedbythechargingofthesamplingcapacitance.ThisisespeciallyimportantwhenusingtheADC121S101tosampleACsignals.Alsoimportantwhensamplingdynamicsignalsisananti-aliasingfilter.

TheoutputformatoftheADC121S101isstraightbinary.CodetransitionsoccurmidwaybetweensuccessiveintegerLSBvalues.TheLSBwidthfortheADC121S101isVA/4096.TheidealtransfercharacteristicisshowninFigure5.Thetransitionfromanoutputcodeof000000000000toacodeof000000000001isat1/2LSB,oravoltageofVA/8192.OthercodetransitionsoccuratstepsofoneLSB.

2014501120145014

FIGURE5.IdealTransferCharacteristic

4.0TYPICALAPPLICATIONCIRCUIT

AtypicalapplicationoftheADC121S101isshowninFigure6.PowerisprovidedinthisexamplebytheNationalSemiconductorLP2950low-dropoutvoltageregulator,avail-ableinavarietyoffixedandadjustableoutputvoltages.Thepowersupplypinisbypassedwithacapacitornetworklo-catedclosetotheADC121S101.BecausethereferencefortheADC121S101isthesupplyvoltage,anynoiseonthesupplywilldegradedevicenoiseperformance.Tokeepnoiseoffthesupply,useadedicatedlinearregulatorforthisde-vice,orprovidesufficientdecouplingfromothercircuitrytokeepnoiseofftheADC121S101supplypin.BecauseoftheADC121S101’slowpowerrequirements,itisalsopossibletouseaprecisionreferenceasapowersupplytomaximizeperformance.Thethree-wireinterfaceisshownconnectedtoamicroprocessororDSP.

FIGURE7.EquivalentInputCircuit

6.0DIGITALINPUTSANDOUTPUTS

TheADC121S101digitalinputs(SCLKandCS)arenotlimitedbythesamemaximumratingsastheanaloginputs.Thedigitalinputpinsareinsteadlimitedto+5.25VwithrespecttoGND,regardlessofVA,thesupplyvoltage.ThisallowstheADC121S101tobeinterfacedwithawiderangeoflogiclevels,independentofthesupplyvoltage.

7.0MODESOFOPERATION

TheADC121S101hastwopossiblemodesofoperation:normalmode,andshutdownmode.TheADC121S101en-tersnormalmode(andaconversionprocessisbegun)whenCSispulledlow.ThedevicewillentershutdownmodeifCSispulledhighbeforethetenthfallingedgeofSCLKafterCSispulledlow,orwillstayinnormalmodeifCSremainslow.Onceinshutdownmode,thedevicewillstaythereuntilCSisbroughtlowagain.Byvaryingtheratiooftimespentinthenormalandshutdownmodes,asystemmaytrade-offthroughputforpowerconsumption,withasamplerateaslowaszero.

7.1NormalMode

ThefastestpossiblethroughputisobtainedbyleavingtheADC121S101innormalmodeatalltimes,sotherearenopower-updelays.Tokeepthedeviceinnormalmodecon-tinuously,CSmustbekeptlowuntilafterthe10thfallingedgeofSCLKafterthestartofaconversion(rememberthataconversionisinitiatedbybringingCSlow).

IfCSisbroughthighafterthe10thfallingedge,butbeforethe16thfallingedge,thedevicewillremaininnormalmode,butthecurrentconversionwillbeaborted,andSDATAwillreturntoTRI-STATE(truncatingtheoutputword).

SixteenSCLKcyclesarerequiredtoreadallofaconversionwordfromthedevice.AftersixteenSCLKcycleshave

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20145013

FIGURE6.TypicalApplicationCircuit

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ADC121S101ApplicationsInformation

(Continued)

elapsed,CSmaybeidledeitherhighorlowuntilthenextconversion.IfCSisidledlow,itmustbebroughthighagainbeforethestartofthenextconversion,whichbeginswhenCSisagainbroughtlow.

AftersixteenSCLKcycles,SDATAreturnstoTRI-STATE.Anotherconversionmaybestarted,aftertQUIEThaselapsed,bybringingCSlowagain.7.2ShutdownMode

Shutdownmodeisappropriateforapplicationsthateitherdonotsamplecontinuously,oritisacceptabletotradethrough-putforpowerconsumption.WhentheADC121S101isinshutdownmode,alloftheanalogcircuitryisturnedoff.

Toentershutdownmode,aconversionmustbeinterruptedbybringingCShighanytimebetweenthesecondandtenthfallingedgesofSCLK,asshowninFigure8.OnceCShasbeenbroughthighinthismanner,thedevicewillentershutdownmode;thecurrentconversionwillbeabortedandSDATAwillenterTRI-STATE.IfCSisbroughthighbeforethesecondfallingedgeofSCLK,thedevicewillnotchangemode;thisistoavoidaccidentallychangingmodeasaresultofnoiseontheCSline.

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FIGURE8.EnteringShutdownMode

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FIGURE9.EnteringNormalMode

Toexitshutdownmode,bringCSbacklow.UponbringingCSlow,theADC121S101willbeginpoweringup(power-uptimeisspecifiedintheTimingSpecificationstable).Thispower-updelayresultsinthefirstconversionresultbeingunusable.Thesecondconversionperformedafterpower-up,however,isvalid,asshowninFigure9.

IfCSisbroughtbackhighbeforethe10thfallingedgeofSCLK,thedevicewillreturntoshutdownmode.ThisisdonetoavoidaccidentallyenteringnormalmodeasaresultofnoiseontheCSline.Toexitshutdownmodeandremaininnormalmode,CSmustbekeptlowuntilafterthe10thfallingedgeofSCLK.TheADC121S101willbefullypowered-upafter16SCLKcycles.

8.0POWERMANAGEMENT

TheADC121S101takestimetopower-up,eitherafterfirstapplyingVA,orafterreturningtonormalmodefromshut-downmode.Thiscorrespondstoone\"dummy\"conversionforanySCLKfrequencywithinthespecificationsinthisdocument.Afterthisfirstdummyconversion,theADC121S101willperformconversionsproperly.NotethatthetQUIETtimemuststillbeincludedbetweenthefirstdummyconversionandthesecondvalidconversion.

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WhentheVAsupplyisfirstapplied,theADC121S101maypowerupineitherofthetwomodes:normalorshutdown.Assuch,onedummyconversionshouldbeperformedafterstart-up,asdescribedinthepreviousparagraph.Thepartmaythenbeplacedintoeithernormalmodeortheshutdownmode,asdescribedinSections7.1and7.2.

WhentheADC121S101isoperatedcontinuouslyinnormalmode,themaximumthroughputisfSCLK/20.ThroughputmaybetradedforpowerconsumptionbyrunningfSCLKatitsmaximumspecifiedrateandperformingfewerconversionsperunittime,raisingtheADC121S101CSlineafterthe10thandbeforethe15thfallofSCLKofeachconversion.AplotoftypicalpowerconsumptionversusthroughputisshownintheTypicalPerformanceCurvessection.Tocalculatethepowerconsumptionforagiventhroughput,multiplythefrac-tionoftimespentinthenormalmodebythenormalmodepowerconsumptionandaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerconsumption.Notethatthecurveofpowerconsumptionvs.throughputisessentiallylinear.Thisisbecausethepowerconsumptionintheshutdownmodeissosmallthatitcanbeignoredforallpracticalpurposes.

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ADC121S101ApplicationsInformation

(Continued)

9.0POWERSUPPLYNOISECONSIDERATIONS

Thechargingofanyoutputloadcapacitancerequirescur-rentfromthepowersupply,VA.Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthesupply.Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.Furthermore,dischargingtheoutputcapaci-tancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresis-tive.Loaddischargecurrentswillcause\"groundbounce\"

noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.Thelargertheoutputcapaci-tance,themorecurrentflowsthroughthediesubstrateandthegreateristhenoisecoupledintotheanalogchannel,degradingnoiseperformance.

Tokeepnoiseoutofthepowersupply,keeptheoutputloadcapacitanceassmallaspractical.Itisgoodpracticetousea100ΩseriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandimprovenoiseperformance.

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ADC121S101PhysicalDimensions

inches(millimeters)unlessotherwisenoted

6-LeadLLP

OrderNumberADC121S101CISDorADC121S101CISDX

NSPackageNumberSDB06A

6-LeadSOT-23

OrderNumberADC121S101CIMF,ADC121S101CIMFX

NSPackageNumberMF06A

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ADC121S101SingleChannel,0.5to1Msps,12-BitA/DConverterNotes

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