Si4430/31/32 ISM TRANSCEIVER Si4430/31/32 ISM收发器
Features 特点
频率范围
● 240–930 MHz (Si4431/32) 唤醒定时器 ● 900–960 MHz (Si4430) 自动频率校正(AFC)
灵敏度 = –121 dBm 上电复位(POR)
输出功率范围 分集式天线和TR开关控制
● +20 dBm Max (Si4432) 可配置的数据包处理程序 ● +13 dBm Max (Si4430/31) 报头检测器
低功耗 TX(发送)和RX(接收) 64位堆栈
● 18.5 mA 接收 低电池检测器 ● 30 mA 在+13 dBm发送时 温度传感器和8位ADC ● 85 mA 在+20 dBm发送时 –40~+85 °C 温度范围
数据速率 = 0.123~256 kbps 集成电压调整器 FSK, GFSK和OOK调制 调频功能 电源 = 1.8~3.6 V 片上晶体调谐 超低功耗关机方式 20脚QFN封装 数字RSSI 省料
Applications
应用
Remote control 遥控
Home security & alarm 家庭安防和报警 Telemetry 遥测
Personal data logging 个人数据记录 Toy control 玩具控制 Tire pressure monitoring 轮胎压力监测 Wireless PC peripherals 无线PC外设
Remote meter reading 远程仪表读数 Remote keyless entry 远程无键输入 Home automation 家庭自动化 Industrial control 工业控制 Sensor networks 传感器网络 Health monitors 健康监控 Tag readers 标签读出器
Description 说明
Silicon Laboratories’ Si4430/31/32 devices are highly integrated, single chip wireless ISM transceivers. The high-performance EZRadioPRO® family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. The Si4430/31/32’s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance.
硅实验室公司的Si4430/31/32器件是高度集成的单片无线ISM收发器, 高性能EZRadioPRO® 系列包含整套发送器、接收器和收发器，使得RF系统设计人员可以选择适合他们应用的最佳的无线电器件。Si4430/31/32的高度集成化降低了材料成本同时简化了总体系统设计，很低的接收灵敏度(–121 dBm)与业内领先的+20 dBm输出功率确保了宽阔的通话范围和改进的链路性能。内置分集式天线和跳频支持可以用来进一步拓展范围和提高性能。
The Si4430/31/32 offers advanced radio features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allowing precise tuning control. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, poweron-reset (POR), and GPIOs further reduce overall system cost and size.
Si4430/31/32提供了先进的无线电特性包括在240–960 MHz范围的频率覆盖和允许进行精确调谐控制的156 Hz或312 Hz的步幅，其它的系统特性如：自动唤醒定时器、低电池检测器、64字节TX/RX堆栈、自动数据包处理、报头检测减少了总的电流消耗，使得可以采用廉价的系统MCU。一个集成的温度传感器、通用ADC、上电复位(POR)和GPIO(通用输入/输出)进一步减少了总的系统成本和尺度。
The Si4430/31/32’s digital receive architecture features a high-performance ADC and DSP based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with global regulations including FCC, ETSI, ARIB, and 802.15.4d regulations.
Si4430/31/32的数字接收结构具有高性能的ADC和基于DSP的执行解调、滤波、数据包处理的调制解调器，提高了灵活性和性能，直接数字发送调制和自动PA功率梯次确保了精确的发送调制，降低了频谱扩展，确保符合全球的法规包括：FCC, ETSI, ARIB和802.15.4d法规。
An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market.
提供了一个易于使用的计算器可以快速进行射频设置，简化了客户的系统设计，减少了投放市场的时间。
Functional Block Diagram 功能方框图
TABLE OF CONTENTS 目录表
Section Page 章节 页数
1. Electrical Specifications 电气规格. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …. 7 1.1. Definition of Test Conditions 测试条件规定 . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2. Functional Description 功能描述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.1. Operating Modes 操作方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3. Controller Interface 控制器接口. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1. Serial Peripheral Interface (SPI) 串行外设接口(SPI) . . . . . . . . . . . . . . . . . . . . . 18 3.2. Operating Mode Control 操作方式控制. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3. Interrupts 中断. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4. System Timing 系统定时. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.5. Frequency Control 频率控制. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. Modulation Options 调制选择. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 32 4.1. Modulation Type 调制类型. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.2. Modulation Data Source 调制数据源. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5. Internal Functional Blocks 内部功能块. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.1. RX LNA 接收低噪声放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2. RX I-Q Mixer 接收I-Q混频器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3. Programmable Gain Amplifier 可编程增益放大器 . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4. ADC 模数转换器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5. Digital Modem 数字调制解调器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.6. Synthesizer 合成器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..38 5.7. Power Amplifier 功率放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..39 5.8. Crystal Oscillator 晶体振荡器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.9. Regulators 调整器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .40 6. Data Handling and Packet Handler 数据处理和数据包处理程序. . . . . . . . . . . . . .41 6.1. RX and TX FIFOs 接收和发送堆栈. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6.2. Packet Configuration 数据包配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.3. Packet Handler TX Mode 数据包处理程序发送方式 . . . . . . . . . . . . . . . . . . . . . . .43 6.4. Packet Handler RX Mode 数据包处理程序接收方式. . . . . . . . . . . . . . . . . . . . . . . 43 6.5. Data Whitening, Manchester Encoding, and CRC 数据白化、曼彻斯特编码和CRC(循环冗余校验) . . . . . . . . . . . . . 46
6.6. Preamble Detector 报头检测器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 46 6.7. Preamble Length 报头长度. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 47 6.8. Invalid Preamble Detector 无效报头检测器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9. Synchronization Word Configuration 同步字配置. . . . . . . . . . . . . . . . . . . . . . . . .47 6.10. Receive Header Check 接收报头检查. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11. TX Retransmission and Auto TX TX重新发送和自动TX . . . . . . . . . . . . . . . . . 48 7. RX Modem Configuration RX调制解调器配置. . . . . . . . . . . . . . . . . . . . . . . . . . . .49 7.1. Modem Settings for FSK and GFSK 调制解调器的FSK和GFSK设置 . . . . . . . . .49 8. Auxiliary Functions 辅助功能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1. Smart Reset 智能复位. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . 50 8.2. Microcontroller Clock 微控制器时钟. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3. General Purpose ADC 通用AD转换器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 8.4. Temperature Sensor 温度传感器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 8.5. Low Battery Detector 低电池检测器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.6. Wake-Up Timer and 32 kHz Clock Source 唤醒定时和32 kHz时钟源. . . . . . . . .56 8.7. Low Duty Cycle Mode 低占空比方式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 8.8. GPIO Configuration GPIO配置. . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . .59 8.9. Antenna Diversity 分集式天线. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.10. RSSI and Clear Channel Assessment RSSI和清晰信道评估 . . . . . . . . . . . . . . 61 9. Reference Design 参考设计. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 62 10. Application Notes and Reference Designs 应用说明和参考设计. . . . . . . . . . . 63 11. Customer Support 客户支持. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12. Register Table and Descriptions 寄存器表和说明. . . . . . . . . . . . . . . . . . . . . . . 64 13. Pin Descriptions: Si4430/31/32 引脚说明: Si4430/31/32. . . . . . . . . . . . . . . . . . 66 14. Ordering Information 订货须知. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . 67 15. Package Markings (Top Marks) 封装标记(顶部标记). . . . . . . . . . . . . . . . . . . . . 68 15.1. Si4730/31/32 Top Mark Si4730/31/32顶部标记 . . . . . . . . . . . . . . . . . . . . . . . . . 68 15.2. Top Mark Explanation 顶部标记解释. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 68 16. Package Outline: Si4430/31/32 封装外形: Si4430/31/32. . . . . . . . . . . . . . . . . . .69 17. PCB Land Pattern: Si4430/31/32 线路板布线样式: Si4430/31/32. . . . . . . . . . . . 70 Document Change List 文件更改列表. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Contact Information 联系信息. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LIST OF FIGURES 图形列表
Figure 1. Si4430/31 RX/TX Direct-Tie Application Example 图1. Si4430/31 RX/TX直接连接应用示例........16
Figure 2. Si4432 Antenna Diversity Application Example 图2. Si4432分集式天线应用示例............16
Figure 3. SPI Timing 图3. SPI定时...................................................................... .....18 Figure 4. SPI Timing—READ Mode 图4. SPI定时—读方式......................................19 Figure 5. SPI Timing—Burst Write Mode 图5. SPI定时—脉冲写方式........................19 Figure 6. SPI Timing—Burst Read Mode 图6. SPI定时—脉冲读方式........................19 Figure 7. State Machine Diagram 图7.机器状态图............................................ ........20 Figure 8. TX Timing 图8 TX定时.............................................................. ......... .......24 Figure 9. RX Timing 图9 RX定时...................................................................... .. ......24 Figure 10. Frequency Deviation 图10.频率偏差............................................ ........ . ..28 Figure 11. Sensitivity at 1% PER vs. Carrier Frequency Offset 图11相对于载波频率偏差的每1%灵敏度.....29
Figure 12. FSK vs GFSK Spectrums 图12 FSK与GFSK频谱对比..............................32 Figure 13. Direct Synchronous Mode Example 图13 直接同步方式示例....................35 Figure 14. Direct Asynchronous Mode Example 图14 直接异步方式示例..................35 Figure 15. Microcontroller Connections 图15.微控制器连接............... ......... .............36 Figure 16. PLL Synthesizer Block Diagram 图16. PLL合成器方框图..........................38 Figure 17. FIFO Thresholds 图17. 堆栈阈值.................................................... .........41
Figure 18. Packet Structure 图18 数据包结构...........................................................42 Figure 19. Multiple Packets in TX Packet Handler 图19 TX数据包处理程序中的多个数据包..........................43
Figure 20. Required RX Packet Structure with Packet Handler Disabled 图20.数据包处理程序关闭时所需的RX数据包结构.....43
Figure 21. Multiple Packets in RX Packet Handler 图21. 在RX数据包处理程序中的多个数据包..........................43
Figure 22. Multiple Packets in RX with CRC or Header Error 图22. RX中带CRC或报头误差的多个数据包 .........44
Figure 23. Operation of Data Whitening, Manchester Encoding, and CRC 图23. 数据白化操作、曼彻斯特编码和CRC .....46
Figure 24. Manchester Coding Example 图24.曼彻斯特编码示例.............................46 Figure 25. Header 图25.报头................................................. .............................. ....48 Figure 26. POR Glitch Parameters 图26.上电复位瞬态干扰参数...............................50 Figure 27. General Purpose ADC Architecture 图27.通用AD转换器结构...................52 Figure 28. Temperature Ranges using ADC8 图28.采用ADC8的温度范围................54 Figure 29. WUT Interrupt and WUT Operation 图29.WUT中断和WUT操作...............57 Figure 30. Low Duty Cycle Mode 图30.低占空比方式................................................58 Figure 31. RSSI Value vs. Input Power 图31. RSSI值与输入功率的关系...................61 Figure 32. TX/RX Direct-Tie Reference Design—Schematic 图32.TX/RX直接连接参考设计图...........62
Figure 33. 20-Pin Quad Flat No-Lead (QFN) 图33. 20脚四列扁平无铅(QFN)封装...................................69
Figure 34. PCB Land Pattern 图34 线路板布线式样.................................................70
LIST OF TABLES 表格列表
Table 1. DC Characteristics1 表格1.直流特性1...........................................................7 Table 2. Synthesizer AC Electrical Characteristics1 表格2.合成器交流电气特性1........8 Table 3. Receiver AC Electrical Characteristics1 表格3.接收器交流电气特性1............9 Table 4. Transmitter AC Electrical Characteristics1 表格4.发送器交流电气特性1........10 Table 5. Auxiliary Block Specifications1 表格5. 辅助块规格1.....................................11 Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) 表格6. 数字IO规格(SDO, SDI, SCLK, nSEL和nIRQ)................12
Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) 表格. GPIO规格(GPIO_0, GPIO_1和GPIO_2)............12
Table 8. Absolute Maximum Ratings 表格8.绝对最大额定值......................................13 Table 9. Operating Modes 表格9.操作方式.................................................................17 Table 10. Serial Interface Timing Parameters 表格10.串行接口定时参数....................18 Table 11. Operating Modes Response Time 表格11.操作方式响应时间......................20 Table 12. Frequency Band Selection 表格12.频带选择...............................................26 Table 13. Packet Handler Registers 表格13.数据包处理寄存器..................................45 Table 14. Minimum Receiver Settling Time 表格14.接收器最小稳定时间....................47 Table 15. POR Parameters 表格15.上电复位参数......................................................50
Table 16. Temperature Sensor Range 表格16.温度传感器范围................................53 Table 17. Antenna Diversity Control 表格17.分集式天线控制....................................60 Table 18. Register Descriptions 表格18.寄存器说明.................................................64 Table 19. Package Dimensions 表格19.封装尺寸.....................................................69 Table 20. PCB Land Pattern Dimensions 表格20.线路板布线尺寸示范.....................71
1. Electrical Specifications 电气规格
Table 1. DC Characteristics1 表格1 直流特性1
Parameter 参数 Supply Voltage Range 电源电压范围 Power Saving Modes 节电方式 Symbol 符号 VDD IShutdown Conditions 条件 Min 最小 1.8 — Typ 典型 3.0 15 Max 最大 3.6 50 Units 单位 V nA RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 RC振荡器, 数字主调整器和低功率数字调整器关闭2 IStandby Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF 低功率数字调整器打开(寄存器值保持), 数字主调整器和RC振荡器关闭 ISleep RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF RC振荡器和低功率数字调整器打开(寄存器值保持), 数字主调整器关闭 ISensor-LBD Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 数字主调整器和低电池检测器打开, 晶振和其它所有块关闭2 ISensor-TS Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 数字主调整器和温度传感器打开, 晶振和其它所有块关闭2 IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled 晶振和数字主调整器打开, 其它所有块关闭. 晶振缓冲器关闭. ITune IRX ITX_+20 Synthesizer and regulators enabled 合成器和调整器打开 txpow[2:0] = 111 (+20 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. 利用硅实验室公司的参考设计, TX电流消耗取决于匹配和线路板布线. txpow[2:0] = 110 (+13 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. 利用硅实验室公司的参考设计, TX电流消耗取决于匹配和线路板布线. txpow[2:0] = 001 (+1 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. 利用硅实验室公司的参考设计, TX电流消耗取决于匹配和线路板布线. — 450 800 nA — 1 — µA — 1 — µA — 1 — µA — 800 — µA TUNE Mode Current 调谐方式电流 RX Mode Current 接收方式电流 TX Mode Current —Si4432 发送方式电流—Si4432 — — — 8.5 18.5 85 — — — mA mA mA TX Mode Current —Si4430/31 ITX_+13 — 30 — mA ITX_+1 — 18 — mA Notes:注释 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the \"Production Test Conditions\" section on page 14. 除非另有说明, 否则所有规格由生产测试保证, 生产测试条件和最大限值列于第14页的―生产测试条件‖一节中. 2. Guaranteed by qualification. Qualification test conditions are listed in the \"Production Test Conditions\" section on page 14. 由技术指标保证, 技术指标测试条件列于第14页的―生产测试条件‖一节中. Table 2. Synthesizer AC Electrical Characteristics1 表格2 合成器交流电气特性1 Parameter 参数 Synthesizer Frequency Range—Si4431/32 Symbol 符号 FSYN Conditions 条件 Min 最小 240 Typ 典型 — Max Units 最大 单位 930 MHz 合成器频率范围—Si4431/32 Synthesizer Frequency FSYN Low Band 低频段, 240–480 MHz High Band 高频段, 480–960 MHz When using external reference signal driving XOUT pin, instead of using crystal. Measured peak-to-peak (VPP) 当采用外部基准信号驱动XOUT引脚时, 不使用晶体, 测量峰-峰值(VPP) Measured from exiting Ready mode with XOSC running to any frequency. Including VCO Calibration. 从退出XOSC以任意频率运行的准备方式开始测量, 包括VCO校正. Integrated over 250 kHz bandwidth (500 Hz lower bound of integration) 在250 kHz带宽上积分(低于500 Hz的积分范围) F = 10 kHz F = 100 kHz F = 1 MHz F = 10 MHz — — 0.7 900 156.25 312.5 — — — — 1.6 960 Hz Hz V MHz Range—Si4430 合成器频率范围—Si4430 Synthesizer Frequency Resolution2 FRES-LB 合成器频率分辨率2 FRES-HB Reference Frequency Input Level2 基准频率输入电平2 fREF_LV Synthesizer Settling Time2 合成器稳定时间2 tLOCK — 200 — µs Residual FM2 残余FM2 FRMS — 2 4 kHzRMS Phase Noise2 相位噪声2 L(fM) — — — — –80 –90 –115 –130 — — — — dBc/Hz dBc/Hz dBc/Hz dBc/Hz Notes: 注释 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the \"Production Test Conditions\" section on page 14. 除非另有说明, 否则所有规格由生产测试保证, 生产测试条件和最大限值列于第14页的―生产测试条件‖一节中. 2. Guaranteed by qualification. Qualification test conditions are listed in the \"Production Test Conditions\" section on page 14. 由技术指标保证, 技术指标测试条件列于第14页的―生产测试条件‖一节中. Table 3. Receiver AC Electrical Characteristics1 表3 接收器交流电气特性1
Parameter 参数 RX Frequency Range—Si4431/32 接收频率范围—Si4431/32 RX Frequency Range—Si4430 接收频率范围—Si4430 RX Sensitivity2 接收灵敏度2 FRX PRX_2 Symbol 符号 FRX (BER < 0.1%) (2 kbps, GFSK, BT = 0.5, f = 5kHz)3 — 900 –121 Conditions 条件 Min 最小 240 — — Typ 典型 — 960 dBm Max 最大 930 MHz Units 单位 MHz PRX_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, f = 20 kHz)3 — –108 — dBm PRX_100 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, f = 50 kHz)3 — –104 — dBm PRX_125 PRX_OOK (BER < 0.1%) (125 kbps, GFSK, BT = 0.5, f = 62.5 kHz) (BER < 0.1%) (4.8 kbps, 350 kHz BW, OOK)3 (BER < 0.1%) (40 kbps, 400 kHz BW, OOK)3 — — — –101 –110 –102 — — — dBm dBm dBm RX Channel Bandwidth3 接收信道带宽3 BER Variation vs Power Level3 BER(位误码率)与功率电平的关系3 LNA Input Impedance3 (Unmatched—measured differentially across RX input pins) LNA(低噪声放大器)阻抗3 (不匹配—在RX输入脚上差分测量) RSSI Resolution RSSI分辨率 1-Ch Offset Selectivity3 信道1偏移量选择性3 2-Ch Offset Selectivity3 信道2偏移量选择性3 3-Ch Offset Selectivity3 信道3偏移量选择性3 BW PRX_RES RIN-RX Up to +5 dBm Input Level 最高达+5 dBm输入电平 915 MHz 868 MHz 433 MHz 315 MHz 2.6 — — 0 620 0.1 kHz ppm — — — — — — — 51–60j 54–63j 89–110j 107–137j ±0.5 –31 –35 –40 — — — — — — — RESRSSI C/I1-CH C/I2-CH Desired Ref Signal 3 dB above sensitivity, BER < 0.1%. Interferer and desired modu-lated with 40 kbps F = 20 kHz GFSK with BT = 0.5, channel spacing = 150 kHz 理想的基准信号, 超过灵敏度3 dB, BER < 0.1%. 干扰信号和采用40 kbps的理想调制 F = 20 kHz GFSK BT = 0.5, 信道间隔= 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5 理想的基准信号, 超过灵敏度3 dB. 干扰信号和采用40 kbps的理想调制 F = 20 kHz GFSK BT = 0.5 Rejection at the image frequency. 在镜像频率处的抑制 IF=937 kHz Measured at RX pins 在RX脚上测量 dB dB dB dB C/I3-CH — –52 –56 –63 –30 — — — dB dB dB dB –54 dBm Blocking at 1 MHz Offset3 在1 MHz偏移量处阻隔3 Blocking at 4 MHz Offset3 在4 MHz偏移量处阻隔3 Blocking at 8 MHz Offset3 在8 MHz偏移量处阻隔3 Image Rejection3 镜像抑制3 Spurious Emissions3 寄生发射3 Notes: 注释 1MBLOCK 4MBLOCK 8MBLOCK ImREJ POB_RX1 — — — — — — — — 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the \"Production Test Conditions\" section on page 14. 除非另有说明, 否则所有规格由生产测试保证, 生产测试条件和最大限值列于第14页的―生产测试条件‖一节中. 2. Receive sensitivity at multiples of 30 MHz may be degraded. If channels with a multiple of 30 MHz are required it is recommended to shift the crystal frequency. Contact Silicon Labs Applications Support for recommendations. 为30 MHz倍数的接收灵敏度可能被降低, 如果需要具有30 MHz倍数的信道, 则建议对晶体频率进行移相, 若要了解这些建议, 请与硅实验室公司的应用支持部联系. 3. Guaranteed by qualification. Qualification test conditions are listed in the \"Production Test Conditions\" section on page 14. 由技术指标保证, 技术指标测试条件列于第14页的―生产测试条件‖一节中. Table 4. Transmitter AC Electrical Characteristics1 表格4 发送器交流电气特性1
Parameter 参数 TX Frequency Range—Si4431/32 发送频率范围—Si4431/32 TX Frequency Range—Si4430 发送频率范围—Si4430 FSK Data Rate2 FSK数据速率2 OOK Data Rate2 OOK数据速率2 Modulation Deviation 调制偏差 FTX DRFSK DROOK Δf1 Δf2 Modulation Deviation Resolution2 调制偏差分辨率2 Output Power Range—Si44323 输出功率范围—Si44323 Output Power Range—Si4430/313 输出功率范围— Si4430/313 ΔfRES Symbol 符号 FTX 860–960 MHz 240–860 MHz 0.123 0.123 ±0.625 ±0.625 — 0.625 900 — — Conditions 条件 Min 最小 240 — 256 40 ±320 ±160 — Typ 典型 — 960 kbps kbps kHz kHz kHz Max 最大 930 MHz Units 单位 MHz PTX +1 — +20 dBm PTX –8 — +13 dBm TX RF Output Steps2 TX RF输出步幅2 TX RF Output Level2 Variation vs. Temperature TX RF输出电平2变化与温度的关系 TX RF Output Level Variation vs. Frequency2 TX RF输出电平变化与频率的关系2 Transmit Modulation Filtering2 发送调制滤波2 Spurious Emissions2 寄生发射2 PRF_OUT PRF_TEMP PRF_FREQ controlled by txpow[2:0] 受txpow[2:0]控制 –40 to +85 C Measured across any one frequency band 在一个频段内测量 Gaussian Filtering Bandwith Time Product 高斯滤波带宽时间积 POUT =+13 dBm, Frequencies <1 GHz 1–12.75 GHz, excluding harmonics 1–12.75 GHz, 不包含谐波 Using reference design TX matching network and filter with max output power. Harmonics reduce linearly with output power. 采用参考设计TX匹配网络和带最大输出功率的滤波器, 谐波减小了输出功率的线性度. — — — 3 2 1 — — — dB dB dB B*T — 0.5 — POB-TX1 POB-TX2 — — — — — — — — –54 –54 –42 –42 dBm dBm dBm dBm Harmonics2 P2HARM P3HARM Notes: 注释 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the \"Production Test Conditions\" section on page 14. 除非另有说明, 否则所有规格由生产测试保证, 生产测试条件和最大限值列于第14页的―生产测试条件‖一节中. 2. Guaranteed by qualification. Qualification test conditions are listed in the \"Production Test Conditions\" section on page 14. 由技术指标保证, 技术指标测试条件列于第14页的―生产测试条件‖一节中. 3. Output power is dependent on matching components and board layout. 输出功率取决于匹配元件和线路板布线. Table 5. Auxiliary Block Specifications1 表格5 辅助块规格
Parameter 参数 Temperature Sensor Accuracy2 温度传感器精度2 Temperature Sensor Sensitivity2 温度传感器灵敏度2 Low Battery Detector Resolution2 低电池检测器分辨率2 Low Battery Detector Conversion Time2 低电池检测器转换时间2 Microcontroller Clock Output Frequency 微控制器时钟输出频率 Symbol 符号 TSA Conditions 条件 After calibrated via sensor offset register tvoffs[7:0] 在通过传感器偏差寄存器tvoffs[7:0]校正后 Min 最小 — Typ 典型 0.5 Max 最大 — Units 单位 °C TSS — 5 — mV/°C LBDRES — 50 — mV LBDCT — 250 — µs FMC Configurable to 30 MHz, 15 MHz, 10 MHz, 4 MHz, 3MHz, 2MHz, 1MHz, or 32.768 kHz 可以配置成30 MHz, 15 MHz, 10 MHz, 4 MHz, 3MHz, 2MHz, 1MHz或32.768 kHz 32.768K — 30M Hz General Purpose ADC Resolution2 通用ADC分辨率2 General Purpose ADC Bit Resolution2 通用ADC位分辨率2 Temp Sensor & General Purpose ADC Conversion Time2 温度传感器和通用ADC转换时间2 ADCENB — 8 — bit ADCRES — 4 — mV/bit ADCCT — 305 — µs 30 MHz XTAL Start-Up time 30 MHz晶振启动时间 t30M 30 MHz XTAL Cap Resolution2 30 MHz晶振电容分辨率 30MRES Using XTAL and board layout in reference design. Start-up time will vary with XTAL type and board layout. 采用参考设计中的晶振和线路板布线, 启动时间将随着晶振型号和线路板布线变化而变化. See \"5.8. Crystal Oscillator\" on page 40 for total load capacitance calculation 关于总的负载电容量计算, 请参看第40页上的\"5.8. 晶体振荡器‖. — 600 — µs — 97 — fF 32 kHz XTAL Start-Up Time2 32 kHz晶振启动时间2 32 kHz XTAL Accuracy using 32 kHz XTAL2 32 kHz晶振精度, 采用32 kHz晶振2 32 kHz Accuracy using Internal RC Oscillator2 32 kHz晶振精度, 采用内部RC振荡器2 POR Reset Time POR复位时间 t32k 32KRES — — 6 100 — — sec ppm Using 20 ppm 32 kHz Crystal 采用 20 ppm 32 kHz的晶振 32KRCRES — 2500 — ppm tPOR — 16 — ms Software Reset Time2 — 100 — µs 软件复位时间2 tsoft Notes: 注释 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the \"Production Test Conditions\" section on page 14. 除非另有说明, 否则所有规格由生产测试保证, 生产测试条件和最大限值列于第14页的―生产测试条件‖一节中. 2. Guaranteed by qualification. Qualification test conditions are listed in the \"Production Test Conditions\" section on page 14. 由技术指标保证, 技术指标测试条件列于第14页的―生产测试条件‖一节中. Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) 表格6 数字IO规格(SDO, SDI, SCLK, nSEL和nIRQ)
Parameter 参数 Rise Time 上升时间 Fall Time 下降时间 Input Capacitance 输入电容 Logic High Level Input Voltage 逻辑高电平 输入电压 Logic Low Level Input Voltage 逻辑低电平 输入电压 Input Current 输入电流 Logic High Level Output Voltage 逻辑高电平 输出电压 Logic Low Level Output Voltage 逻辑低电平 输出电压 Symbol 符号 TRISE TFALL CIN VIH VIL IIN VOH VOL Conditions 条件 0.1 x VDD to 0.9 x VDD, CL= 5 pF 0.9 x VDDto 0.1 x VDD,CL= 5 pF 0 Parameter 参数 VDD to GND VDD至GND(地) Instantaneous VRF-peak to GND on TX Output Pin 在TX输出脚上相对于GND的瞬时VRF峰值 Sustained VRF-peak to GND on TX Output Pin 在TX输出脚上相对于GND的维持VRF峰值 Voltage on Digital Control Inputs 在数字控制输入端上的电压 Voltage on Analog Inputs 在模拟输入端上的电压 RX Input Power RX输入功率 Operating Ambient Temperature Range TA 操作环境温度范围 Thermal Impedance 热阻JA Junction Temperature 结温 TJ Storage Temperature Range 贮藏温度范围 TSTG Value 值 –0.3, +3.6 –0.3, +8.0 –0.3, +6.5 –0.3, VDD+ 0.3 –0.3, VDD+ 0.3 +10 –40 to +85 30 +125 –55 to +125 Unit 单位 V V V V V dBm C C/W C C Note: Stresses beyond those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device. 注释: 超过―绝对最大额定值‖中所列具的值的应力可能导致器件的永久损坏, 这些仅仅是在应力额定值, 并不表示按照在规格书的操作章节中额定值或超过额定值时器件可正常运行.长时间承受绝对最大额定值条件可能影响器件的可靠性, 如果不连接适当的负载就接通功率放大器, 则它可能受损害. TX匹配网络设计将影响在TX输出脚上的TX VRF峰值. 注意: 它是对ESD敏感的器件. 1.1. Definition of Test Conditions 测试条件规定 Production Test Conditions: 生产测试条件 TA = +25 °C VDD = +3.3 VDC Sensitivity measured at 919 MHz 灵敏度是在919 MHz频率处测得的 TX output power measured at 915 MHz 发送输出功率是在919 MHz频率处测得的 External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC Production test schematic (unless noted otherwise) All RF input and output levels referred to the pins of the Si4430/31/32 (not the RF module) 外部基准信号(XOUT) = 1.0 VPP，频率为30 MHz，中心在0.8 VDC左右 生产测试原理图(除非另有说明) Qualification Test Conditions: 技术指标测试条件 TA = –40 to +85 °C VDD = +1.8 to +3.6 VDC Using TX/RX Split Antenna reference design or production test schematic All RF input and output levels referred to the pins of the Si4430/31/32 (not the RF module) 采用TX/RX分支天线参考设计或生产测试原理图 所有RF输入和输出电平是参照Si4430/31/32(而非RF模块)的引脚 2. Functional Description 功能描述 The Si4430/31/32 are ISM wireless transceivers with continuous frequency tuning over their specified bands which encompasses from 240–960 MHz. The wide operating voltage range of 1.8–3.6 V and low current consumption makes the Si4430/31/32 an ideal solution for battery powered applications. Si4430/31/32是在240–960 MHz范围规定频段上具有连续的调频的ISM无线收发器, 1.8–3.6 V的宽的工作电压范围和电流消耗低使得Si4430/31/32成为电池驱动应用的理想的解决方案. The Si4430/31/32 operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert the 2-level FSK/GFSK/OOK modulated receive signal to a low IF frequency. Si4430/31/32以时分复用的(TDD)收发器方式工作，器件交替发送和接收数据包，该器件利用单转换混频器把2级FSK/GFSK/OOK调制的接收信号转换成较低的中频信号。 Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is then output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO is generated by an integrated VCO and Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency and frequency deviation at any frequency between 240–960 MHz. The transmit FSK data is modulated directly into the data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. 在可编程增益放大器(PGA)之后，信号通过可以允许在内置DSP中进行滤波、解调、限幅和数据包处理的高性能ADC而转换成数字域，提高了基于模拟结构的接收器的性能和灵活性。解调的信号然后通过一个可编程的GPIO或者通过标准SPI总线读64位RX堆栈而输出至系统MCU，单个高精度本机振荡器(LO)用于发送和接收方式，因为发送器和接收器不同时运行。LO由一个集成VCO和分数N PLL合成器构成，合成器设计成支持可配置的数据速率、输出频率和在240–960 MHz之间的任意频率处的频偏。发送FSK数据被直接调制到数据流中，并且可以通过高斯低通滤波器整形以消除多余的频谱成分。 The Si4432’s PA output power can be configured between +1 and +20 dBm in 3 dB steps, while the Si4430/31's PA output power can be configured between –8 and +13 dBm in 3 dB steps. The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and rampdown control to reduce unwanted spectral spreading. The +20 dBm power amplifier of the Si4432 can also be used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve comparable performance. The Si4430/31/32 supports frequency hopping, TX/RX switch control, and antenna diversity switch control to extend the link range and improve performance. Si4432的PA(可编程放大器)输出功率可以在+1和+20 dBm之间设置，步幅为3 dB，而Si4430/31的PA输出功率可以在–8和+13 dBm之间设置，步幅为3 dB。PA是单端的，可以进行方便的天线匹配并且具有较低的材料成本。PA兼有自动的逐级增加和逐级减小控制以减小多余的频谱扩展。Si4432的+20 dBm功率放大器也可用于补偿低成本的性能降低、性能较差的天线或者由于较小的波形因数带来的尺寸限制的天线，同类的解决方案需要较大的和昂贵的外部PA来实现差不多的性能，Si4430/31/32支持跳频、TX/RX切换控制、分集式天线切换控制，扩展了链路范围并改善了性能。 The Si4430/31/32 is designed to work with a microcontroller, crystal, and a few external components to create a very low cost system as shown Figure 1. Voltage regulators are integrated on-chip which allows for a wide operating supply voltage range from +1.8 to +3.6 V. A standard 4-pin SPI bus is used to communicate with an external microcontroller. Three configurable general purpose I/Os are available. A complete list of the available GPIO functions is shown in \"8. Auxiliary Functions\" on page 50 and includes microcontroller clock output, Antenna Diversity, POR, and various interrupts. Si4430/31/32设计成可配合微控制器、晶体和一些外接元件工作，构成如图1所示的成本很低的系统，电压调整器是片上集成的，允许在+1.8 ~ +3.6 V之间的较宽的工作电源电压范围。一个 标准的4脚SPI总线用于与外部微控制器进行通讯，可以采用三个可配置的通用I/O端口，完整的、有效的GPIO功能列表如第50页上的\"8.辅助功能\"中所示, 该列表包含微控制器时钟输出、分集式天线、POR(上电复位)和各种中断。 The application shown in Figure 1 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference design is available from Silicon Laboratories applications support. 如图1中所示的应用是针对采用TX/RX直接连接配置而不采用TX/RX切换的系统设计的，大多数低功耗应用将采用这一配置，完整的直接连接参考设计可以从硅实验室公司的应用支持部获取。 For applications seeking improved performance in the presence of multipath fading antenna diversity can be used. Antenna diversity support is integrated into the Si4430/31/32 and can improve the system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support. 在出现多通道衰减分集式天线时，为了寻求改进的性能可以使用它。 分集式天线支持集成在Si4430/31/32中，在出现这些衰减条件时，可以改善系统链路预算8–10 dB，大幅度地扩大了范围，完整的分集式天线参考设计可以从硅实验室公司的应用支持部获取。 Figure 1. Si4430/31 RX/TX Direct-Tie Application Example 图1. Si4430/31 RX/TX直接连接应用示例 Figure 2. Si4432 Antenna Diversity Application Example 图2. Si4432 分集式天线应用示例 2.1. Operating Modes 操作方式 The Si4430/31/32 provides several operating modes which can be used to optimize the power consumption for a given application. Depending upon the system communication protocol, an optimal trade-off between the radio wake time and power consumption can be achieved. Table 9 summarizes the operating modes of the Si4430/31/32. In general, any given operating mode may be classified as an active mode or a power saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode, all can be dynamically selected by sending the appropriate commands over the SPI. An ―X‖ in any cell means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF, without noticeably impacting the current consumption. The SPI circuit block includes the SPI interface hardware and the device register space. The 32 kHz OSC block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector. Si4430/31/32提供了几种操作方式，可用于针对给定的应用使功耗最优化，根据系统通信协议，可以实现在无线唤醒时间和功耗之间的最佳平衡。表格9汇总了Si4430/31/32的操作方式，一般来说，任何给定的操作方式可以分为工作方式和省电方式。此表格表明了在每个相应的方式开通哪些功能块。除了关机方式以外，所有方式可以通过SPI发送相应的指令进行动态选择。在格子中的―X‖意味着在给定的操作方式，功能块可以被独立编程为打开或关闭而不会显著影响电流消耗，SPI电路块包含SPI接口硬件和器件寄存器空间，32 kHz OSC(振荡器)块包含32.768 kHz RC振荡器或32.768 kHz晶体振荡器以及唤醒定时器，AUX (辅助块)包含温度传感器、通用ADC和低电池检测器。 Table 9. Operating Modes 表格9. 操作方式 Mode Name 方式名称 Circuit Blocks 电路块 Digital LDO 数字 LDO OFF (Register contents lost) 关闭(寄存器内容丢失) ON (Register contents retained) 打开(寄存器内容保存) SPI 32 kHz OSC AUX 30 MHz XTAL PLL PA RX IVDD OFF OFF OFF OFF OFF OFF OFF 15 nA SHUT-DOWN 关机 STANDBY 待机 SLEEP 睡眠 SENSOR 传感器 READY 准备 TUNING 调谐 TRANSMIT 发送 RECEIVE 接收 ON ON ON ON ON ON ON OFF ON X X X X X OFF X ON X X X X OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF ON 450 nA 1 µA 1 µA 800 µA 8.5 mA 30 mA* 18.5 mA *Note: Using Si4430/31 at +13 dBm using recommended reference design. *注意: 利用推荐的参考设计, 按+13 dBm来使用Si4430/31. 3. Controller Interface 控制器接口 3.1. Serial Peripheral Interface 串行外设接口 (SPI) The Si4430/31/32 communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL. Si4430/31/32通过一个标准的3线SPI接口: SCLK, SDI和nSEL与主MCU进行通信. The host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA) as demonstrated in Figure 3. The 7-bit address field is used to select one of the 128, 8-bit control registers. The R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1 it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the Si4430/31/32 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 10. The SCLK rate is flexible with a maximum rate of 10 MHz. 主MCU可以在SDO输出脚上读来自器件的数据, SPI处理是一个由读写(R/W)选择位后面跟着7位地址字段(ADDR)和8位数据字段(DATA)构成的16位序列, 如图3中所示. 7位地址字段用于选择128个8位控制寄存器之一, R/W选择位确定SPI处理是一个读还是写处理. 如果R/W = 1, 它表示一个写处理, 当R/W = 0时表示一个读处理. 每隔八个时钟周期, 内容(地址或数据)被锁存在Si4430/31/32中, SPI接口的定时参数如表格10中所示, SCLK速率是灵活可变的, 最大速率为10 MHz. Figure 3. SPI Timing 图3. SPI定时 Table 10. Serial Interface Timing Parameters 表格10. 串行接口定时参数 To read back data from the Si4430/31/32, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the SDI pin when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 4. After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup. 若要从Si4430/31/32中读回数据, 则在需要读的寄存器的7位地址后的R/W位必须设置为0. 当R/W = 0时, 在SDI引脚上的在7位地址字段后的8位数据字段被忽略, 下面的八个SCLK信号的负边沿跳变将传送出选中的寄存器的内容. 从选中的寄存器中读出的数据将出现在SDO输出脚上, 读功能如图4所示. 在读功能完成后, SDO引脚将维持在逻辑1或逻辑0状态, 这取决于传送出的最后的数据位(D0), 当nSEL变为高时, SDO输出脚将被内部上拉电阻拉高. Figure 4. SPI Timing—READ Mode 图4. SPI 定时—读方式 The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers without having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An example burst write transaction is illustrated in Figure 5 and a burst read in Figure 6. As long as nSEL is held low, input data will be latched into the Si4430/31/32 every eight SCLK cycles. SPI接口包含一个脉冲读/写方式, 它可以读/写顺次的寄存器而不必重新发送, 当nSEL位维持低并且继续发送SCLK脉冲时, SPI接口将自动增加地址并对下一个地址读出或写入. 脉冲写处理的 示例如图5所示, 脉冲读处理的示例如图6所示. 只要nSEL保持低, 则每隔八个SCLK周期, 输入数据将锁存到Si4430/31/32中. Figure 5. SPI Timing—Burst Write Mode 图5. SPI定时—脉冲写方式 Figure 6. SPI Timing—Burst Read Mode 图6. SPI定时—脉冲读方式 3.2. Operating Mode Control 操作方式控制 There are four primary states in the Si4430/31/32 radio state machine: SHUTDOWN, IDLE, TX, and RX (see Figure 7). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. \"Register 07h. Operating Mode and Function Control 1\" controls which operating mode/state is selected with the exception of SHUTDOWN which is controlled by SDN pin 20. The TX and RX state may be reached automatically from any of the IDLE states by setting the txon/rxon bits in \"Register 07h. Operating Mode and Function Control 1\". Table 11 shows each of the operating modes with the time required to reach either RX or TX mode as well as the current consumption of each mode. 在Si4430/31/32机器无线状态中有四种主要的状态: 关机、闲置、发送和接收(参看图7), 关机状态完全关闭无线电通信使电流消耗降至最低, 空闲状态有5种不同的配置/选项, 可以选择用于针对应用需要使芯片最优化. ―寄存器07h. 操作方式和功能控制1‖控制除了由SDN(20)脚控制的关机以外所选择的操作方式/状态. 发送和接收状态可以通过设置―寄存器07h. 操作方式和功能控制1‖中的txon/rxon位从闲置状态自动进入, 表格11表明了各种操作方式和进入接收或发送方式所需的时间以及各方式的电流消耗. The Si4430/31/32 includes a low-power digital regulated supply (LPLDO) which is internally connected in parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin). This common digital supply voltage is connected to all digital circuit blocks including the digital modem, crystal oscillator, SPI, and register space. The LPLDO has extremely low quiescent current consumption but limited current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. The main digital regulator is automatically enabled in all other modes. Si4430/31/32包含一个低功耗的数字调整电源(LPLDO), 内部与数字主调整器的输出并联(外部 在VR_DIG引脚上提供), 此公共数字电源电压与所有的数字电路块包括: 数字调制解调器、晶体振荡器、SPI和寄存器空间链接， LPLDO具有极低的静态电流消耗但有限的电流供应能力; 它只能在空闲-待机和空闲-睡眠方式使用, 在所有其它方式, 数字主调整器被自动打开. 图7. 机器状态图 Table 11. Operating Modes Response Time 表格11. 操作方式响应时间 3.2.1. SHUTDOWN State 关机状态 The SHUTDOWN state is the lowest current consumption state of the device with nominally less than 15 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. 关机状态是器件电流消耗最低的状态, 通常小于15 nA的电流消耗, 关机状态可以通过把SDN脚(20脚)驱动为高而进入, 除了在关机状态以外, SDN脚在其它所有状态下应当维持为低, 在关机状态, 寄存器的内容丢失并且无法访问SPI, 当芯片与电源连接时, 在SDN的下降沿将发出一个上电复位. 3.2.2. IDLE State 空闲状态 There are five different modes in the IDLE state which may be selected by \"Register 07h. Operating Mode and Function Control 1\". All modes have a tradeoff between current consumption and response time to TX/RX mode. 在空闲状态有五种不同的方式可以通过―寄存器07h.操作方式和功能控制1‖选择, 所有方式都有一个在电流消耗和TX/RX方式响应时间之间的平衡. This tradeoff is shown in Table 11. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 这种平衡如表格11中所示, 在POR(上电复位)事件、SWRESET(软件复位)或从关机状态中退出后, 芯片将默认进入空闲-准备方式, 在POR事件后, 中断寄存器必须被读出以正确地进入睡眠、传感器或待机方式，并且正确控制32 kHz时钟。 3.2.2.1. STANDBY Mode 待机方式 STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled to maintain the register values. In this mode the registers can be accessed in both read and write mode. The STANDBY mode can be entered by writing 0h to \"Register 07h. Operating Mode and Function Control 1\". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 待机方式具有电流消耗最低的五种空闲状态，仅开启LPLDO以保存寄存器值。在这种方式，寄存器可以读和写方式访问，待机方式可以通过把0h写入―寄存器07h. 操作方式和功能控制1‖而进入。如果发生了一个中断(亦即nIRQ脚 = 0), 则中断寄存器必须被读出以实现最低的电流消耗, 另外, 在这种方式ADC不应当被选择为GPIO的输入, 因为它将引起太大的电流消耗. 3.2.2.2. SLEEP Mode 睡眠方式 In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See \"8.6. Wake-Up Timer and 32 kHz Clock Source\" on page 56 for more information on the Wake-Up-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in \"Register 07h. Operating Mode and Function Control 1\". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 在睡眠方式, LPLDO与唤醒定时器一起被开通, 此定时器可以按照规定的间隔时间唤醒无线电装置. 若要了解关于唤醒定时器的更多的信息, 请参看56页上的\"8.6.唤醒定时器和32 kHz时钟源\". 睡眠方式可以通过把―寄存器07h. 操作方式和功能控制1‖中的enwt 设置为= 1 (40h)而进入. 如果发生了一个中断(亦即nIRQ脚 = 0), 则中断寄存器必须被读出以实现最低的电流消耗, 另外, 在这种方式ADC不应当被选择为GPIO的输入, 因为它将引起太大的电流消耗. 3.2.2.3. SENSOR Mode 传感器方式 In SENSOR mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in \"Register 07h.Operating Mode and Function Control 1\". See \"8.4. Temperature Sensor\" on page 53 and \"8.5. Low Battery Detector\" on page 55 for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 在传感器方式，除了LPLDO和唤醒定时器以外，低电池检测器、温度传感器或这两者也能开通，低电池检测器可以通过设置\"寄存器 07h.操作方式和功能控制1\"中的enlbd = 1而开通。若要了解关于这些特性的更多信息, 请参看53页上的\"8.4. 温度传感器\"和55页上的\"8.5. 低电池检测器\如果发生了一个中断(亦即nIRQ脚 = 0), 则中断寄存器必须被读出以实现最低的电流消耗。 3.2.2.4. READY Mode 准备方式 READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in \"Register 07h. Operating Mode and Function Control 1\". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled in ―Register 62h. Crystal Oscillator Control and Test.‖ To exit READY mode, bufovr (bit 1) of this register must be set back to 0. 准备方式设计成可以提供具有合理的电流消耗的TX方式的快速过渡时间，在该方式下，晶体振荡器始终开通，通过消除晶振启动时间减小了切换到TX或RX方式所需的时间。准备方式可以通过设置\"寄存器 07h.操作方式和功能控制1\"中的xton = 1而开通。若要达到最低的电流消耗状态，则晶体振荡缓冲器应当在―寄存器62h.晶体振荡控制和测试‖中设置成关闭，若要退出准备方式，该寄存器的bufovr (位1)必须设置回0。 3.2.2.5. TUNE Mode 调谐方式 In TUNE mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to TX mode as the PLL will remain locked but it results in the highest current consumption. 在调谐方式，除了其它功能块在空闲状态被开启外，PLL(锁相环)保持开通，当PLL保持锁定时，这将给TX方式提供最快的响应， 但会造成最高的电流消耗。 This mode of operation is designed for frequency hopping spread spectrum systems (FHSS). TUNE mode is entered by setting pllon = 1 in \"Register 07h. Operating Mode and Function Control 1\". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. 此操作方式是针对跳频扩展频谱系统(FHSS)设计的，调谐方式可以通过设置\"寄存器 07h.操作方式和功能控制1\"中的pllon = 1而开通。该方式不必把xton设置为1，内部机器状态会自动开启晶体振荡器。 3.2.3. TX State 发送状态 The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in \"Register 07h. Operating Mode and Function Control 1\". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit. 当寄存器 07h.操作方式和功能控制1\"中的txon位设置为1时，可以从空闲方式进入发送状态，一个内置的排序器会关注从开启晶体振荡器到打开可编程放大器的状态之间转换所需的所有行动，当通过设置txon位从待机方式转换到发送方式时，下列事件序列将自动产生。 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is ―0‖, default value is ―1‖). 5. Wait until PLL settles to required transmit frequency (controlled by an internal timer). 6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer). 7. Transmit packet. Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled. 1. 开启数字主LDO和模拟LDO电源。 2. 开启晶体振荡器并等待至准备(由一个内部定时器控制)。 3. 开启PLL(锁相环)。 4. 校正VCO(当vcocal位为―0‖时，这一步骤将跳过)。 5. 等待PLL稳定至所需的发送频率(由内部定时器控制)。 6. 开启功率放大器并等待电源电压上升完成(由内部定时器控制)。 7. 发送数据包。 在这一顺序中的某些步骤可以根据在设置txon位之前芯片所配置的空闲方式而省略。默认情况是， 每当PLL开启时，VCO和PLL就被校正。 3.2.4. RX State 接收状态 The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in \"Register 07h. Operating Mode and Function Control 1\". A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: 当寄存器 07h.操作方式和功能控制1\"中的rxon位设置为1时，可以从空闲方式进入发送状态，一个内置的排序器会关注从空闲方式之一到接收状态之间转换所需的所有行动，当通过设置rxon位从待机方式转换到接收方式时，下列事件序列将自动产生： 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is ―0‖, default value is ―1‖). 5. Wait until PLL settles to required receive frequency (controlled by an internal timer). 6. Enable receive circuits: LNA, mixers, and ADC. 7. Enable receive mode in the digital modem. 1. 开启数字主LDO和模拟LDO电源。 2. 开启晶体振荡器并等待至准备(由一个内部定时器控制)。 3. 开启PLL(锁相环)。 4. 校正VCO(当vcocal位为―0‖时，这一步骤将跳过)。 5. 等待PLL稳定至所需的接收频率(由内部定时器控制)。 6. 开启接收电路: LNA(低噪声放大器), 混频器和ADC。 7. 在数字调制解调器中开启接收方式。 Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and CRC. 根据无线电装置的配置，下面的所有或某些功能将被数字调制解调器自动执行：AGC、AFC(可选)、更新状态寄存器、位同步、数据包处理(可选)包括同步字、报头检查和CRC(循环冗余校验)。 3.2.5. Device Status 器件状态 The operational status of the chip can be read from \"Register 02h. Device Status\". 芯片的工作状态可以从\"寄存器02h. 器件状态\"中读出。 3.3. Interrupts 中断 The Si4430/31/32 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at anytime in the Interrupt Status registers. 当发生某些事件时，Si4430/31/32能够发出一个中断信号，芯片通过把nIRQ输出脚设置为LOW = 0来通知微控制器发生了一个中断事件。当如下所示的一个或多个中断事件(与中断状态位相对应)发生时，此中断信号将产生。nIRQ脚将保持低直至微控制器读出包含有效的中断状态位的中断状态寄存器(寄存器03h–04h)，nIRQ输出信号然后被复位直至检测到下一个状态变化。中断必须通过中断使能寄存器(寄存器05h–06h)中相应的使能位而开通，当微控制器读出中断状态寄存器时，所有开通的中断位将被清零。如果当事件发生时中断没有开通，则它将不触发nIRQ脚，但该状态仍可以在任何时候从中断状态寄存器中读出。 See ―AN440: EZRadioPRO Detailed Register Descriptions‖ for a complete list of interrupts. 关于中断的完整列表，请查看―AN440: EZRadioPRO 详细的寄存器说明‖。 3.4. System Timing 系统定时 The system timing for TX and RX modes is shown in Figures 8 and 9. The figures demonstrate transitioning from STANDBY mode to TX or RX mode through the built-in sequencer of required steps. The user only needs to program the desired mode, and the internal sequencer will properly transition the part from its current mode. 发送和接收的系统定时如图8和9中所示，这些图表明了通过所需步骤的内置排序器从待机方式到发送或接收方式的转换，用户只需要编程所需的方式，内部排序器将正确地从其当前方式转换到该部分。 The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround time is desired. VCO(压控振荡器)将会在每次频率变化或上电时自动校正，PLL T0时间是考虑到VCO的偏压稳定，PLL TS时间是PLL的稳定时间，默认稳定时间为100 µs。在各种情况下PLL T0, PLL CAL和PLL TS的总时间为200 µs。在某些应用中，为了更快的转换时间，PLL T0时间和PLL CAL可以跳过，如果需要更快的转换时间，则请与应用支持部联系。 图8. TX定时 图9. RX定时 3.5. Frequency Control 频率控制 For calculating the necessary frequency register settings it is recommended that customers use Silicon Labs’ Wireless Design Suite (WDS) or the EZRadioPRO Register Calculator worksheet (in Microsoft Excel) available on the product website. These methods offer a simple method to quickly determine the correct settings based on the application requirements. The following information can be used to calculated these values manually. 为了计算所需的频率寄存器设置，建议客户采用在产品网站上可以获得的硅实验室公司的无线设计套件(WDS)或EZRadioPRO寄存器计算工作表(Microsoft Excel格式)。这些方法提供了根据应用要求快速确定正确设置的简单方法，下列信息可以用来手工计算这些值。 3.5.1. Frequency Programming 频率编程 In order to receive or transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the Si4430/31/32. The Si4431/32 and Si4430 cover different frequencies. This section discusses the frequency range covered by all EZRadioPRO devices. Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3rd order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is as follows: 为了接收或发送RF信号， 所需的信道频率fcarrier必须编程到Si4430/31/32中，Si4431/32 和 Si4430覆盖不同的频率。本节讨论所有EZRadioPRO器件所覆盖的频率范围。注意：此频率是所需信道的中心频率不是LO(本机振荡)频率。此载波频率是采用作为基准频率的10 MHz和(三阶) ΔΣ调制器的时钟由分数N合成器产生的，此调制器采用以64000为模的累加器，此设计是为了获得所需的合成器的频率分辨率，反馈回路的总的标度比由整数部分(N)和分数部分(F)构成，在一般意义上，合成器的输出频率如下： The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in \"3.5.4. Frequency Deviation\" on page 27. Also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency is shown below: 分数部分(F)由三个不同的值：载波频率(fc[15:0])、频率偏置Offset (fo[8:0])和频率偏差(fd[7:0])确定，由于合成器的高分辨率和高回路带宽，FSK调制应用于回路内部并根据输入的数据改变F来完成，这将在27页上的\"3.5.4.频率偏差\"中作进一步的讨论。另外，可以增加一个固定的偏置来细调载波频率并抵消晶体的容许误差。为了简单起见，假定仅fc[15:0]寄存器将确定分数部分，载波频率的选择方程如下所示： Add R/W 73 74 75 76 77 Function/Description 功能/描述 R/W Frequency Offset 1 频率偏置1 R/W Frequency Offset 2 频率偏置2 R/W Frequency Band Select 频段选择 D7 fo[7] D6 fo[6] D5 fo[5] D4 fo[4] D3 fo[3] D2 fo[2] D0 POR Def. fo[1] fo[0] 00h fo[9] fo[8] 00h 35h BBh 80h D1 fc[15] fc[7] sbsel fc[14] fc[6] hbsel fc[13] fc[5] fb[4] fc[12] fc[4] fb[3] fc[11] fc[3] fb[2] fb[1] fb[0] R/W Nominal Carrier Frequency 1 额定载波频率1 fc[10] fc[9] fc[8] fc[2] fc[1] fc[0] R/W Nominal Carrier Frequency 0 额定载波频率0 The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in \"Register 75h. Frequency Band Select.\" This effectively partitions the entire 240–960 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the formula above. Table 12 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation: 整数部分(N)由fb[4:0]确定, 另外, 输出频率可以通过把÷2除法器与输出端连接而减半, 此除法器不在回路内部, 是由\"寄存器75h.频段选择\"中的hbsel位控制的. 这使得整个240–960 MHz频率范围分成两个独立的频段: 高频段, hbsel = 1, 和低频段hbsel = 0。fb[4:0]的有效范围为0~23，如果一个更高的值写入此寄存器，它将默认为值23。整数部分具有增加24的固定偏置，如上述公式中所示，表格12表明了相应频段的fb[4:0]的选择情况。 在选择了fb (N)之后，分数部分可以用下列方程求得： fb and fc are the actual numbers stored in the corresponding registers. fb和fc是贮存在相应寄存器中的实际数。 Table 12. Frequency Band Selection 表格12 频段选择 The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture; therefore, no frequency reprogramming is required when using the same TX frequency and switching between RX/TX modes. 当进入接收方式时，芯片将自动变换合成器的频率降至937.5 kHz (30 MHz ÷ 32)以获取正确的中频(IF)，低侧注入用于接收混频结构中，因此当采用相同的TX频率并且在RX/TX方式之间切换时，无需对频率进行再编程。 3.5.2. Easy Frequency Programming for FHSS 跳频系统的简易频率编程 While Registers 73h–77h may be used to program the carrier frequency of the Si4430/31/32, it is often easier to think in terms of ―channels‖ or ―channel numbers‖ rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size. 当寄存器73h–77h可用于编程Si4430/31/32的载波频率时，在―信道‖或―信道数‖方面进行考虑比在绝对频率Hz值方面进行考虑更为方便，另外，可能存在一些希望通过编程单个寄存器来改变频率的一些定时非常重要的应用(譬如：跳频系统)，一旦信道步幅大小被设定，则频率可以通过与信道数对应的单个寄存器进行修改。如上所述利用寄存器73h–77h首先设置标称频率，寄存器79h和7Ah然后被用于设置相对于标称设置的信道步幅大小和信道数。跳频步幅大小(fhs[7:0])是按10 kHz增量设置的，最大信道步幅为2.56 MHz，跳频信道选择寄存器然后选择基于步幅倍数的信道。 For example, if the nominal frequency is set to 900 MHz using Registers 73h–77h, the channel step size is set to 1 MHz using \"Register 7Ah. Frequency Hopping Step Size,\" and \"Register 79h. Frequency Hopping Channel Select\" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. 例如：如果标称频率利用寄存器73h–77h被设置为900 MHz，信道步幅利用\"寄存器7Ah. 跳 频步幅\"被设置为1 MHz， \"寄存器79h. 跳频信道选择\"被设置为5d, 则最终的载波频率将为905 MHz。一旦标称频率和信道步幅被编程到寄存器中，则为了改变频率，你只需要编程fhch[7:0]寄存器。 Add 79 R/W R/W Function/Description 功能/描述 Frequency Hopping Channel Select 跳频信道选择 Frequency Hopping Step Size 跳频步幅 D7 fhch[7] D6 fhch[6] D5 fhch[5] D4 fhch[4] D3 D2 D1 fhch[1] fhch[3] fhch[2] POR Def. fhch[0] 00h D0 7A R/W fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h 3.5.3. Automatic State Transition for Frequency Change 针对频率变化的自动状态转换 If registers 79h or 7Ah are changed in either TX or mode, the state machine will automatically transition the chip back to TUNE, change the frequency, and automatically go back to either TX or RX. This feature is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in turn reduces microcontroller activity, reducing current consumption. The exception to this is during TX FIFO mode. If a frequency change is initiated during a TX packet, then the part will complete the current TX packet and will only change the frequency for subsequent packets. 如果寄存器79h或7Ah在TX或RX方式被修改，则机器状态将自动使芯片返回到TUNE(调谐)来改变频率并自动回到TX或RX。此特性对于减少跳频系统中所需的SPI指令的条数很有用处，这反过来减少了微控制器的活跃度，降低了电流消耗。例外情况是在TX堆栈方式期间，如果频率变化是在TX数据包期间开始的，那么这一部分将完成当前的TX数据包并且仅改变后续数据包的频率。 3.5.4. Frequency Deviation 频率偏差 The peak frequency deviation is configurable from ±0.625 to ±320 kHz. The Frequency Deviation (Δf) is controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. 最大频偏可以在±0.625 ~ ±320 kHz范围内设置，频偏(Δf)受频偏寄存器(fd)、地址71和72h控制，与载波频率设置无关。 When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviate from the nominal center channel carrier frequency by ±Δf: 当开启时，无论hbsel位的设置如何(高频段或低频段)，频偏的分辨率将保持625 Hz的增量，当采用频率调制时，载波频率将与标称中心信道的载波频率偏差±Δf: 图10 频偏 The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see \"4.1. Modulation Type\" on page 32 for further details. 上面的方程将用于计算所需的频率偏差，需要时，频率调制也可以被关闭以便获得处于信道中心频率的未调制的载波信号；关于进一步的详情，请参看32页上的\"4.1.调制类型\"。 Add 71 72 R/W Function/Description 功能描述 Modulation Mode Control 2 R/W 调制方式控制2 R/W Frequency Deviation 频偏 D7 trclk[1] fd[7] D6 trclk[0] fd[6] D5 dtmod[1] fd[5] D4 dtmod[0] fd[4] D3 eninv fd[3] D2 D1 D0 modtyp[0] fd[0] POR Def. 00h 20h fd[8] modtyp[1] fd[2] fd[1] 3.5.5. Frequency Offset Adjustment 频率偏置调整 When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. It is not possible to have both AFC and offset as internally they share the same register. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset it is necessary to take the twos complement of the positive offset number. The offset can be calculated by the following: 当AFC(自动频率控制)关闭时，频率偏置可以通过寄存器73h和74h中的fo[9:0]进行手动调整，但无法同时拥有AFC和偏置，因为它们内部共享同一寄存器。频率偏置调整和AFC都可以通过移动合成器本机振动频率来实现，该寄存器是一个带符号的寄存器以便获得一个负偏置，对于正的偏置数必须采用2的补码，该偏置可以通过下列公式计算 The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band mode the fo[9:0] register should be set to 360h. 高频段的调整范围为±160 kHz，低频段的调整范围为±80 kHz，譬如：要计算高频段的+50 kHz的偏置，则方式fo[9:0]应当设置为0A0h，对于高频段的–50 kHz的偏置，fo[9:0]寄存器应当设置为360h。 Add R/W Function/Description 功能/描述 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 00h 00h 73 74 R/W Frequency Offset 频率偏置 R/W Frequency Offset 频率偏置 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[9] fo[0] fo[8] 3.5.6. Automatic Frequency Control 自动频率控制(AFC) All AFC settings can be easily obtained from the settings calculator. This is the recommended method to program all AFC settings. This section is intended to describe the operation of the AFC in more detail to help understand the trade-offs of using AFC.The receiver supports automatic frequency control (AFC) to compensate for frequency differences between the transmitter and receiver reference frequencies. These differences can be caused by the absolute accuracy and temperature dependencies of the reference crystals. Due to frequency offset compensation in the modem, the receiver is tolerant to frequency offsets up to 0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled, the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of receiver sensitivity (at 1% PER) versus carrier offset and the impact of AFC are illustrated in Figure 11. 所有AFC设置可以从设置计算器中方便地获得, 这是编程所有的AFC设置的推荐方法, 本节想更加详细地描述AFC的操作以帮助理解采用AFC的得失. 接收器支持自动频率控制(AFC) 以补偿在发送器和接收器基准频率之间的频率偏差. 这些差值可能是由基准晶振的绝对精度和温度的变化关系引起，由于调制解调器中的频偏补偿，因此当AFC关闭时，接收器可以容忍最大为中频带宽的0.25倍的频偏。当AFC打开时，接收到的信号将处于中频滤波器的通带中心，提供在最大为中频带宽的0.35倍的频偏范围内的最佳的灵敏度和选择性，接收器灵敏度(在1% PER条件下)与载波偏差之间的平衡以及AFC的影响如图11中所示。 Figure 11. Sensitivity at 1% PER vs. Carrier Frequency Offset 图11 在1% PER(位误码率)时灵敏度与载波频率偏置的关系 When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened from 40 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see \"6.7. Preamble Length\" on page 47). The AFC corrects the detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble is detected, the AFC will freeze for the remainder of the packet. In multi-packet mode the AFC is reset at the end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop includes a bandwidth limiting mechanism improving the ejection of out of band signals. When the AFC loop is enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in register 2Ah. 当AFC打开时，报头长度需要足够长以便使得AFC稳定下来。一般来说，1字节的报头足以使得AFC稳定下来。关闭AFC则允许报头从40位缩短至32位，注意：当AFC关闭时，报头仍然必须足够长以便使得接收器稳定并且检测到报头(参看47页上的\"6.7. 报头长度\")。AFC通过改变分数N PLL(锁相环)的频率来纠正检测到的频偏，当检测到报头时，AFC将冻结数据包的其余部分。在多数据包方式，AFC在每个数据包的末尾复位并且重新采集频偏至下一个数据包。AFC回路包括一个改善带外信号喷发的带宽限制机构，当AFC回路打开时，其牵引范围由位于寄存器2Ah中的带宽限制值(AFCLimiter)确定。 AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Register Calculator spreadsheet. The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is controlled from afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured frequency error and is advised for most applications. Every bit added will half the feedback but will require a longer preamble to settle. AFC限制寄存器是一个无符号寄存器，其值可以从EZRadioPRO寄存器计算器电子表格中获得。 在报头被检测到之前反馈至分数N PLL(锁相环)的误差校正量受afcgearh[2:0]的控制，默认值000 与测得频率误差的100%反馈有关，并建议用于大多数应用中，每个增加的位将使反馈减半，但将需要一个更长的报头加以稳定。 The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two bit times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time is allowed to settle the Fractional-N PLL to the new frequency before the next frequency error is measured. The duration of the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling). If shwait[2:0] is programmed to 3'b000, there is no AFC correction output. AFC按下列方式工作，输入信号的频率误差在两位时间内被测得，然后它通过分数N PLL校正本机振荡器，在进行此校正后和在测量下一个频率误差之前需要一些时间使得N PLL(锁相环)稳定在新的频率。在检测到报头之前的AFC周期的持续时间可以用shwait[2:0]进行编程，我们建议采用默认值001，它把AFC周期设定为4个位时间(2个用于测量，2个用于稳定)。如果shwait[2:0]被编程为3'b000，则没有AFC校正输出。 The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the following formula: AFC校正值可以从寄存器2Bh中读出，该值可以用下列公式转换成kHz： AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0] Frequency Correction 频率校正 RX AFC disabled AFC关闭 AFC enabled AFC打开 Freq Offset Register 频偏寄存器 AFC TX Freq Offset Register 频偏寄存器 Freq Offset Register 频偏寄存器 3.5.7. TX Data Rate Generator TX数据速率发生器 The data rate is configurable between 0.123–256 kbps. For data rates below 30 kbps the ‖ txdtrtscale‖ bit in register 70h should be set to 1. When higher data rates are used this bit should be set to 0. 数据速率可以在0.123–256 kbps设置，对于低于30 kbps的数据速率，寄存器70h中的―txdtrtscale‖位应当设置为1, 当采用较高的数据速率时, 此位应当设置为0。 The TX date rate is determined by the following formula in kbps: TX数据速率由下列公式确定(单位: kbps)： For data rates higher than 100 kbps, Register 58h should be changed from its default of 80h to C0h. Non-optimal modulation and increased eye closure will result if this setting is not made for data rates higher than 100 kbps. The txdr register is only applicable to TX mode and does not need to be programmed for RX mode. The RX bandwidth which is partly determined from the data rate is programmed separately. 对于高于100 kbps的数据速率，寄存器58h应当从其默认值80h改成C0h。如果该设置不是 按照高于100 kbps的数据速率进行的，则非最佳调制和闭眼增加现象将产生，txdr寄存器仅适 用于TX方式，无需针对RX方式进行编程，由数据速率部分确定的RX带宽是单独编程的。 Add 6E 6F R/W Function/Description 功能/描述 D7 D6 D5 txdr[13] txdr[5] D4 txdr[12] txdr[4] D3 txdr[11] txdr[3] D2 txdr[10] txdr[2] D1 txdr[9] txdr[1] D0 txdr[8] txdr[0] POR Def. 0Ah 3Dh R/W TX Data Rate TX数据速率 1 R/W TX Data Rate TX数据速率 0 txdr[15] txdr[14] txdr[7] txdr[6] 4. Modulation Options 调制选择 4.1. Modulation Type 调制类型 The Si4430/31/32 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 12 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering. The frequency domain plots demonstrate the spectral benefit of GFSK over FSK. The type of modulation is selected with the modtyp[1:0] bits in \"Register 71h. Modulation Mode Control 2\". Note that it is also possible to obtain an unmodulated carrier signal by setting modtyp[1:0] = 00. Si4430/31/32支持三种不同的调制选择: 高斯频移键控(GFSK)、频移键控(FSK)、开关键控(OOK). GFSK是推荐的调制类型，因为它提供最好的性能和最干净的调制频谱。图12展现了对于64 kbps数据速率来说FSK和GFSK之间的差异，时域图表明了高斯滤波的效果。 频域图表明了GFSK比起FSK的频谱优点，调制类型是用\"寄存器71h. 调制方式控制 2\"中的modtyp[1:0]位来选择的。注意：也可以通过设置modtyp[1:0] =00来获得一个未调制的载波信号。 modtyp[1:0] 00 01 10 11 GFSK Modulation Source 调制源 Unmodulated Carrier 未调制的载波 OOK FSK (enable TX Data CLK when direct mode is used) (当采用直接方式时, 开启TX数据时钟) 图12 FSK与GFSK频谱对比 4.2. Modulation Data Source 调制数据源 The Si4430/31/32 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtmod[1:0] field in \"Register 71h. Modulation Mode Control 2\". 可以配置Si4430/31/32获取来自三种不同来源: 堆栈方式、直接方式和PN9的某个引脚的调制数据，在直接方式，TX调制数据可以从几个不同的引脚获取，这些选项是通过\"寄存器71h. 调制方式控制 2\"中的dtmod[1:0]字段设置的。 Add R/W 71 Function/Description 功能/描述 D7 trclk[1] D6 trclk[0] D5 dtmod[1] D4 dtmod[0] D3 eninv D2 D1 D0 modtyp[0] POR Def. 00h R/W Modulation Mode Control 2 调制方式控制 2 dtmod[1:0] 00 01 10 11 fd[8] modtyp[1] Data Source 数据源 Direct Mode using TX/RX Data via GPIO pin (GPIO configuration required) 通过GPIO脚利用TX/RX数据的直接方式(需要GPIO配置) Direct Mode using TX/RX Data via SDI pin (only when nSEL is high) 通过SDI脚利用TX/RX数据的直接方式(仅当nSEL为高时) FIFO Mode 堆栈(先进先出)方式 PN9 (internally generated 由内部产生) 4.2.1. FIFO Mode 堆栈方式 In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The FIFOs are accessed via \"Register 7Fh. FIFO Access,\" and are most efficiently accessed with burst read/write operation as discussed in \"3.1. Serial Peripheral Interface (SPI)\" on page 18. In TX mode, the data bytes stored in FIFO memory are \"packaged\" together with other fields and bytes of information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler Registers (see Table 13 on page 45). If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are automatically added to the bytes stored in FIFO memory). For further information on the configuration of the FIFOs for a specific application or packet size, see \"6.Data Handling and Packet Handler\" on page 41. 在堆栈方式, 发送和接收数据贮存在集成FIFO存储器中. 此堆栈可以通过\"寄存器7Fh. FIFO Access\"访问, 可以采用18页上的\"3.1. 串行外设接口(SPI)\"中所讨论的脉冲读/写操作最有效地访问. 在TX方式, 贮存在FIFO存储器中的数据字节与其它信息字段和字节一起―打包‖构成最终的发送数据包结构。这些其它的可能字段包括报头、同步字、标题、CRC校验和等，在TX方式数据包结构的配置由自动数据包处理程序(若开启)以及各数据包处理寄存器(45页上的表13)确定。如果自动数据包处理程序关闭，则整个所需的数据包结构应当装入FIFO存储器中，无其它字段(如: 报头或同步字被自动加入贮存在FIFO存储器中的字节). 若要了解特定的应用或数据包大小的FIFO配置的信息, 请参看41页上的\"6.数据处理和数据包处理程序\"。 In RX mode, only the bytes of the received packet structure that are considered to be \"data bytes\" are stored in FIFO memory. Which bytes of the received packet are considered \"data bytes\" is determined by the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see Table 13 on page 45). If the Automatic Packet Handler is disabled, all bytes following the Sync word are considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not desired, the preamble detection threshold and Sync word still need to be programmed so that the RX Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received data may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can be quite useful during application development. 在接收方式，只有被看作是\"数据字节\"的收到的数据包结构的字节被贮存在FIFO存储器中，收到的数据包的哪些字节被看作是\"数据字节\"是由自动数据包处理程序(若开启)以及各数据包处理寄存器(45页上的表13)确定。如果自动数据包处理程序关闭，则在同步字后的所有字节被看作是数据字节并贮存在FIFO存储器中。因此，即使自动数据包处理操作不是想要的，报头检测阈值和同步字仍然需要编程使得RX调制解调器知道何时开始把数据装入堆栈中。当此堆栈在RX方式下被使用时，可以通过适当编程GPIO引脚为RXDATA输出脚仍可以直接观察到(以实时方式)所有收到的数据；这一点在应用开发中可能非常有用。 When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid interrupt occurs. The chip will return to the IDLE mode state programmed in \"Register 07h. Operating Mode and Function Control 1\". For example, the chip may be placed into TX mode by setting the txon bit, but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the STANDBY state. 当处于堆栈方式时，并且当ipksent或ipkvalid中断发生时，芯片将自动退出TX 或RX状态，芯片将返回到在\"寄存器 07h. 操作方式和功能控制1\"中编程的空闲方式状态。例如：可以通过把txon位置位并且pllon位也被置位使得芯片处于TX方式。芯片将发送堆栈的所有内容并且发生ipksent中断。当此中断事件发生时，芯片将清除txon位并返回到pllon位设置状态所示的TUNE(调谐)方式，如果寄存器07h(除了最初txon外)中的其它位没有被置位，则芯片将返回到待机状态。 In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Register 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully receiving a packet, but will remain in RX mode. The microcontroller will need to decide on the appropriate subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or preamble detect. 在RX方式，如果ipkvalid发生并且rxmpk位(RX多数据包位，SPI 寄存器08h位[4])没有被置位，则rxon位将被清零。当rxmpk位被置位时，该器件在成功收到数据包后将退出RX状态，但仍保持在RX方式。微控制器将需要根据如：CRC产生的中断、数据包有效或报头检测之类的信息来决定采取适当的后续行动。 4.2.2. Direct Mode 直接方式 For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. 对于在MCU或其它基带芯片内部执行数据包处理的传统系统来说，采用堆栈可能不理想，对于这种场合，提供了一个完全旁路堆栈的直接方式。 In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in \"real time\" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for use as the TX Data input function. 在TX直接方式，TX调制数据加给芯片的输入脚并被\"实时\"处理(亦即：不贮存在某个寄存器中稍后发送)，许多引脚可以配置用做TX数据输入功能。 Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field. 而且，如果需要GFSK调制，则可能需要一个额外的引脚用于TX时钟输出功能(FSK只需要 TX数据输入脚)，TX数据源的两个选择在dtmod[1:0]字段中提供，TX数据时钟源的各种配置可以通过trclk[1:0]字段选择。 trclk[1:0] 00 01 10 11 TX/RX Data Clock Configuration TX/RX数据时钟配置 No TX Clock (only for FSK) 无TX时钟(仅针对FSK) TX/RX Data Clock is available via GPIO (GPIO needs programming accordingly as well) TX/RX数据时钟通过GPIO提供(GPIO也需要相应编程) TX/RX Data Clock is available via SDO pin (only when nSEL is high) TX/RX数据时钟通过SDO脚提供(仅当nSEL为高时) TX/RX Data Clock is available via the nIRQ pin TX/RX数据时钟通过nIRQ脚提供 The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing purposes. SPI寄存器71h中的eninv位将使TX数据反相，这对于诊断和测试目的可能最有用处。 In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC. In RX direct mode, the chip must still acquire bit timing during the Preamble, and thus the preamble detection threshold (SPI Register 35h) must still be programmed. Once the preamble is detected, certain bit timing functions within the RX Modem change their operation for optimized performance over the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode; however, if the Sync word is absent then the skipsyn bit in SPI Register 33h must be set, or else the bit timing and tracking function within the RX Modem will not be configured for optimum performance. 在RX直接方式，RX数据和RX时钟可以针对GPIO引脚的直接(实时)输出进行编程，微控制器然后可以处理RX数据而不利用RFIC的FIFO或数据包处理功能。在RX直接方式，芯片仍然必须在报头期间获得位定时，因此报头检测阈值(SPI寄存器35h)仍然必须编程。一旦检测到报头，在RX调制解调器内部的某些位定时功能在数据包的剩余时间内按照最优化性能来改变它们的操作。在RX直接方式，同步字不必出现在数据包中，但是若同步字不出现，则SPI寄存器33h中的skipsyn位必须置位，否则在RX调制解调器内的位定时和跟踪功能将不是按最佳性能配置的。 4.2.2.1. Direct Synchronous Mode 直接同步方式 In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock signal as an input and respond by providing one bit of TX Data back to the RFIC, synchronous with one edge of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of the RFIC; no TX Data bits are made available at the input of the RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). 在TX直接方式，芯片可以按同步或异步调制方式配置。在直接同步方式，配置RFIC提供一个TX时钟信号作为至提供TX数据流的外部器件的输出，此TX时钟信号是一个频率等于预编程数据速率的方波。外部调制源(如: MCU)必须接受此TX时钟信号为一个输入并通过向RFIC提供与TX时钟信号的边沿同步的1位TX数据来响应。在这种方式，来自外源的TX数据输入流的速率受编程的RFIC的数据速率控制；TX数据位不在RFIC的输入端提供直至为另一个TX时钟信号周期所要求。外源提供的TX数据位以实时方式直接发送(亦即: 不在内部贮存而稍后发送)。 All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in the next section, there are limits on modulation types in TX direct asynchronous mode. 所有调制类型(FSK/GFSK/OOK)在TX直接同步方式有效，在TX直接异步方式有对调制类型的限制，将在下一节中进行讨论。 4.2.2.2. Direct Asynchronous Mode 直接异步方式 In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream. Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need for a TX Clock output signal from the RFIC, as there is no synchronous \"handshaking\" between the RFIC and the external data source. 在TX直接异步方式，RFIC不再控制TX数据输入流的数据速率，其数据速率仅由外部TX数据源控制；RFIC只是按照其提供的数据速率接收施加给TX数据输入脚的数据，这意味着不再需要来自RFIC的TX时钟输出信号，因为在RFIC和外部数据源之间没有同步\"握手\"。 The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). 外源提供的TX数据位是以实时方式直接传送的(亦即: 不在内部贮存而稍后发送)。 It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode. The chip still internally samples the incoming TX Data stream to determine when edge transitions occur; however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course, it is still necessary to program the desired peak frequency deviation.) 当在TX直接异步方式下工作时不必编程数据速率参数，芯片仍然对输入的TX数据流进行内部采样以确定边沿跳变何时发生，但是不是按照预编程的数据速率采集数据，芯片现在是按照其最大可能的过采样速率对输入的TX数据流进行内部采样。这使得芯片精确地确定位边沿跳变的定时而不事先知道数据速率(当然，仍然必须编程所需的峰值频率偏差)。 Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming data. One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required. The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to GFSK). 在TX直接异步方式，只有FSK和OOK调制类型有效；GFSK调制无法在异步方式使用，这是由于RFIC不了解提供的数据速率，因此不能确定适用于输入数据的高斯低通滤波函数。 此方式的一个优点是它节省了微控制器引脚，因为不需要TX时钟输出功能。 此方式的主要缺点是FSK所占用频带宽带的增加(与GFSK相比)。 图13 直接同步方式示例 图14 直接异步方式示例 4.2.2.3. Direct Mode using SPI or nIRQ Pins 利用SPI或nIRQ引脚的直接方式 In certain applications it may be desirable to minimize the connections to the microcontroller or to preserve the GPIOs for other uses. For these cases it is possible to use the SPI pins and nIRQ as the modulation clock and data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW then the function of the pin will be SPI data output. If the pin is high and trclk[1:0] is 10 then during RX and TX modes the data clock will be available on the SDO pin. If trclk[1:0] is set to 11 and no interrupts are enabled in registers 05 or 06h, then the nIRQ pin can also be used as the TX/RX data clock. 在某些应用中，可能需要使得微控制器的连接降至最低或保留GPIO做其它用途，对于这些场合，可以采用SPI和nIRQ引脚作为调制时钟和数据，通过编程trclk = 10，SDO脚可以配置为数据时钟。如果nSEL脚为低，则该脚的功能是SPI数据输出。如果该脚为高并且trclk[1:0]为10，则在RX和TX方式期间，数据时钟可以在SDO脚上提供。如果trclk[1:0]被设置为11并且寄存器05或06h中不开启中断，那么nIRQ脚也可用做TX/RX数据时钟。 The SDI pin can be configured to be the data source in both RX and TX modes if dtmod[1:0] = 01. In a similar fashion, if nSEL is LOW the pin will function as SPI data-in. If nSEL is HIGH then in TX mode it will be the data to be modulated and transmitted. In RX mode it will be the received demodulated data. Figure 15 demonstrates using SDI and SDO as the TX/RX data and clock: 若dtmod[1:0] = 01，则SDI脚在RX和TX两种方式下可以配置为数据源，与之类似，若nSEL为低，则该脚可以用做SPI数据输入。若nSEL为高，则在TX方式，它将是被调制或传送的数据。在RX方式，它将是接收到的解调数据，图15表明了把SDI和SDO用做TX/RX数据和时钟： 图15 微控制器连接 If the SDO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by programming Reg 0Eh bit 3. 如果SDO脚不用于数据时钟，则可以通过编程Reg 0Eh位3把它编程为中断功能。 4.2.3. PN9 Mode PN9方式 In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having to provide data. 在此方式，TX数据是采用伪随机(PN9序列)位发生器由内部产生的，此方式的主要目的是用做测试方式来观察调制的频谱而不必提供数据。 5. Internal Functional Blocks 内部功能块 This section provides an overview some of the key blocks of the internal radio architecture. 本节提供内部无线结构的主要功能块的概况。 5.1. RX LNA 接收低噪声放大器 Depending on the part, the input frequency range for the LNA is between 240–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal performance. 根据器件不同，LNA的输入频率范围在240–960 MHz之间，LNA提供噪声系数足够低的增益以抑制后级的噪声。LNA具有受模拟增益控制(AGC)算法控制的单步增益控制，AGC算法调整LNA 和PGA的增益，使得接收器能够以最佳的性能处理至+5 dBm灵敏度的信号电平。 In the Si4431, the TX and RX may be tied directly. See the TX/RX direct-tie reference design available on the Silicon Labs website. for more details. When the direct tie is used, the lna_sw bit in ―Register 6Dh. TX Power‖ must be set. 在Si4431中, TX和RX可以直接连接起来，关于更多详情，请查看在硅实验室公司网站上所提供的TX/RX直接连接参考设计，当采用直接连接时，在―寄存器 6Dh. TX电源‖中的lna_sw位必须置位。 5.2. RX I-Q Mixer RX I-Q混频器 The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programmable gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO output. LNA的输出内部馈给接收混频器的输入端，接收混频器以I-Q混频器方式实现，它可以提供至可编程增益放大器的I和Q信道输出。混频器由两个双平衡混频器构成，其RF输入端被并行驱动，本机振荡器(LO)输入端以正交方式驱动，单个的I和Q中频(IF)输出端驱动可编程增益放大器。接收本振信号由工作频率在240–960 MHz之间的集成VCO和PLL合成器提供，必需的正交本振信号是从分频器的VCO输出端引出的 5.3. Programmable Gain Amplifier 可编程增益放大器 The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC algorithm in the digital modem. 可编程增益放大器(PGA)提供必要的增益使得信号电平提升至ADC的动态范围内，PGA也必须具有足够的增益切换使得较大的输入信号可以保证最大至–20 dBm的线性RSSI范围，PGA具有受数字调制解调器中的AGC算法控制的3 dB步幅。 5.4. ADC The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of band blockers. 利用具有低功耗和高动态范围的模数转换器(ADC)把放大的IQ中频信号转换成数字信号，ADC的带通响应提供了对带外干扰的额外抑制。 5.5. Digital Modem 数字调制解调器 Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the following functions: 利用高性能ADC可以进行信道滤波、镜像抑制以及在数字域中进行解调，减小了面积而增加了灵活性。数字调制解调器执行下列功能： Channel selection filter 信道选择滤波 RX解调 报头检测 TX modulation TX调制 RX demodulation AGC 自动增益控制 无效报头检测 无线信号强度指示(RSSI) 自动频率补偿(AFC) 循环冗余校验(CRC) Preamble detector Invalid preamble detector Radio signal strength indicator (RSSI) Automatic frequency compensation (AFC) Packet handling including EZMAC® features 数据包处理包括EZMAC®特性 Cyclic redundancy check (CRC) The digital channel filter and demodulator are optimized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. 数字信道滤波器和解调器是按照极低功耗进行最优化并可以灵活配置，支持的调制类型为GFSK、FSK和OOK。可以配置信道滤波器支持从620 kHz到2.6 kHz频率范围的带宽，支持从0.123到 256 kbps的各种数据速率，AGC算法利用针对快速响应时间进行优化的先进的控制回路以数字方式实现。 The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection. 可以配置的报头检测器用来改善同步字检测的可靠性，只有当检测到有效的报头时同步字检测器才开启，显著减少了虚假检测的可能性。 The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. 接收信号强度指示器(RSSI)提供了测量调谐信道上收到的信号强度的手段，RSSI的分辨率为0.5 dB，此高分辨率的RSSI能够进行精确的信道功率测量便于执行清晰信道评估(CCA)、载波检测(CS)和讲话前倾听(LBT)功能。 Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic frequency control (AFC) in receive mode. A comprehensive programmable packet handler including key features of Silicon Labs’ EZMAC is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication. 由晶振误差带来的频率失调可以通过在接收方式开启数字自动频率控制(AFC)来补偿，一个完整的包含硅实验室公司的EZMAC的主要特性的可编程数据包处理程序集成在其中，形成了从对等网络到网状网络的各种通信拓扑结构，数据包标题的广泛的可编程能力可以进行先进的数据包滤波，最终能够执行传送、群和点对点通信的混合。 A wireless communication channel can be corrupted by noise and interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. 无线通信信道可能遭受噪声和干扰的破坏，因此了解接收到的数据没有差错是很重要的，循环冗余校验(CRC)用于检测在每个数据包中是否存在错误位，CRC被计算并且附在每个发送的数据包的末尾，并且由接收器核对以确认没有错误发生，数据包处理程序和CRC能够显著减轻系统微控制器的负载，允许采用简单一些的和更廉价的微控制器。 The digital modem includes the TX modulator which converts the TX data bits into the corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may not be adjusted to other values. 数字调制解调器包含TX调制器，它把TX数据位转换成数字调制值的相应的数据流，调制值与ΣΔ调制器的分数输入值相加，此调制方法形成了对频偏的高精度分辨率，采用高斯滤波器支持GFSK，极大地降低了邻近信道的能量，对于所有编程的数据速率默认的带宽时间积(BT)为0.5，但它不可调整为其它值。 5.6. Synthesizer 合成器 An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided on-chip. The Si4431/32 and Si4430 cover different frequencies. This section discusses the frequency range covered by all EZRadioPRO devices. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider which results in very precise accuracy and control over the transmit deviation. 能够在240–960 MHz频率范围内工作的集成的ΣΔ分数N PLL(锁相环)合成器是片上提供的，Si4431/32和Si4430覆盖不同的频率，本节讨论所有EZRadioPRO器件所覆盖的频率范围。采用ΣΔ合成器有许多优点；它提供了在选择数据速率、偏差、信道频率和信道间隔方面的灵活性。发送调制通过分频器在数字域中直接施加给回路，能够很精确地控制发送偏差。 Depending on the part, the PLL and ΣΔ modulator scheme is designed to support any desired frequency and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123–256 kbps, and the frequency deviation can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in \"3.5. Frequency Control\" on page 25. 根据器件设计了PLL和ΣΔ调制方案以支持频率分辨率为156.25 Hz (低频段) 或312.5 Hz (高频段)和在240–960 MHz频率范围内所需的频率和信道间隔，发送数据速率可以在0.123–256 kbps之间编程，频偏可以在±1–320 kHz之间编程，这些参数可以通过如25页上的\"3.5.频率控制\"中所示的寄存器进行调整。 图16 锁相环合成器方框图 The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired output frequency band. The modulus of the variable divide-by-N divider stage is controlled dynamically by the output from the ΣΔ modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz. PLL的基准频率为10 MHz，PLL利用一个差分L-C VCO(压控振荡器)和集成的片上电感，VCO的输出端跟着一个可配置的分频器，该分频器把信号频率降至所需的输出频段，可变÷N分频级的模数受ΣΔ调制器输出动态控制，调谐分辨率足以调整至指定频率，在240–960 MHz频率范围内的最大精度为312.5 Hz。 5.6.1. VCO 压控振荡器 The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in \"Register 75h. Frequency Band Select.\" In receive mode, the LO frequency is automatically shifted downwards by the IF frequency of 937.5 kHz, allowing transmit and receive operation on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external VCO components are required. The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register. VCO的输出被自动分频至正确的输出频率，取决于\"寄存器5h. 频段选择\"中的hbsel和fb[4:0]字段，在接收方式，本振频率被937.5 kHz的IF频率自动降频，使得发送和接收操作处于相同频率。VCO把谐振电感和变容二极管集成在一起，因此不需要外部的VCO元件。VCO利用一个电容单元来覆盖指定的很宽的频率范围，每当合成器开启时，此电容单元就自动校正，在某些快速跳频应用中，这可能是不需要的，因此可以通过设置适当的寄存器来跳过VCO校正。 5.7. Power Amplifier 功率放大器 The Si4432 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between –1 and +20 dBm. The Si4431/4430 contains a PA which is capable of transmitting output levels between –8 to +13 dBm. The PA design is single-ended and is implemented as a two stage class CE amplifier with a high efficiency when transmitting at maximum power. The PA efficiency can only be optimized at one power level. Si4432包含一个内部集成的功率放大器(PA)，它能够以–1和+20 dBm之间的输出电平进行发送，Si4431/4430包含一个PA，它能够以–8 ~+13 dBm之间的输出电平进行发送。PA设计为单端的，采用两级CE类放大器来实现，当以最大功率发射时具有高的效率，PA效率只能在某一功率电平下进行最优化。 Changing the output power by adjusting txpow[2:0] will scale both the output power and current but the efficiency will not remain constant. The PA output is ramped up and down to prevent unwanted spectral splatter. 通过调整txpow[2:0]改变输出功率将使输出功率和电流同比改变，但效率不会保持恒定，PA输出将逐渐上升或下降以防止有害的邻频道干扰。 In the Si4431, the TX and RX may be tied directly. See the TX/RX direct-tie reference design available on the Silicon Labs website. for more details. When the direct tie is used, the lna_sw bit in ―Register 6Dh. TX Power‖ must be set. 在Si4431中, TX和RX可以直接连接起来，关于更多详情，请查看在硅实验室公司网站上所提供的TX/RX直接连接参考设计，当采用直接连接时，在―寄存器 6Dh. TX电源‖中的lna_sw位必须置位。 5.7.1. Output Power Selection 输出功率选择 The output power is configurable in 3 dB steps with the txpow[2:0] field in \"Register 6Dh. TX Power.\" Extra output power can allow the use of a cheaper smaller antenna, greatly reducing the overall BOM cost. The higher power setting of the chip achieves maximum possible range, but of course comes at the cost of higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery life may be insignificant. Contact Silicon Labs Support for help in evaluating this tradeoff. 输出功率可以用\"寄存器 6Dh. TX功率\"中的txpow[2:0]字段进行配置，步幅为3 dB。额外的输出功率允许使用更廉价的、更小的天线，可以极大地降低总的材料成本。芯片的较高功率设置可以实现最大可能的通信范围，但这当然是以较高的TX电流消耗作为代价。不过，这取决于系统的 负载周期，电池寿命的影响可能是次要的。可与硅实验室公司联系以帮助评价这种得失。 5.8. Crystal Oscillator 晶体振荡器 The Si4430/31/32 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required offchip is the 30 MHz crystal. Si4430/31/32包含一个集成的30 MHz晶体振荡器，当采用一个合适的并联谐振晶体时，它具有小于600 µs的快速启动时间。该设计为差分方式，所需的晶体负载电容集成在片上，把外接元件的数量降至最少，默认情况是，芯片外只需要一个30 MHz晶体。 The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the xlc[6:0] field of \"Register 09h. 30 MHz Crystal Oscillator Load Capacitance.\" The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0]. 晶体负载电容可以采用数字方式编程使得晶体适应各种负载电容要求并且调整晶体振荡器的频率，晶体负载电容的调谐是通过\"寄存器09h. 30 MHz晶体振荡器负载电容\"的xlc[6:0]字段编程的，总的内部电容量为12.5 pF，并按照大约127个步幅(97fF/步)进行调整，xtalshift位提供粗略的频率偏移，但xlc[6:0]不是二进制。 The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the onchip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled. 晶体频率调整可用于补偿晶体振荡偏差，利用片上温度传感器和合适的控制软件，晶体对温度的 依赖关系可以被消除。 The typical value of the total on-chip capacitance Cint can be calculated as follows: 总的片上电容Cint的典型值可以用下式计算： Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning. Additional information on calculating Cext and crystal selection guidelines is provided in ―AN417: Si4x3x Family Crystal Oscillator.‖ 注意：粗略偏移位xtalshift对于xlc[6:0]不是二进制关系，晶体两端等效的总负载电容Cload可以通过把所有外部线路板寄生电容Cext与Cint相加来计算，如果Cint的最大值 (16.3 pF)不够，则可以增加外部电容进行精确调谐，关于计算Cext的其它资讯以及晶体选择指导意见在―AN417: Si4x3x系列晶体振荡器‖中提供。 If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in \"Register 73h. Frequency Offset 1\" and \"Register 74h. Frequency Offset 2\ 如果AFC关闭，则合成器频率可以按照25页上的\"3.5.频率控制\"中讨论的方法对\"寄存器73h. 频率偏置1\" 和\"寄存器74h.频率偏置2\"中的频率偏置字段fo[9:0]编程来作进一步的调整。 The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration are discussed further in \"8.2. Microcontroller Clock\" on page 51. 晶体振荡频率在内部进行分频，可以通过GPIO引脚之一输出至微控制器用做系统时钟，在这一方式，整个系统只需要一个晶体振荡器，材料成本节省了，可以提供的时钟频率和GPIO配置将在51页上的\"8.2.微控制器时钟\"中作进一步的讨论。 The Si4430/31/32 may also be driven with an external 30 MHz clock signal through the XOUT pin. When driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0. Si4430/31/32也可以通过XOUT引脚采用外部30 MHz时钟信号驱动，当采用外部基准驱动或采用TCXO时, XTAL负载电容寄存器应当设置为0。 Add 09 R/W Function/Description 功能/描述 R/W Crystal Oscillator Load Capacitance 晶体振荡器负载电容 D7 xtalshift D6 xlc[6] D5 xlc[5] D4 xlc[4] D3 xlc[3] D2 xlc[2] D1 xlc[1] D0 xlc[0] POR Def. 7Fh 5.9. Regulators 调整器 There are a total of six regulators integrated onto the Si4430/31/32. With the exception of the digital regulator, all regulators are designed to operate with only internal decoupling. The digital regulator requires an external 1 µF decoupling capacitor. All regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V. The output stage of the of PA is not connected internally to a regulator and is connected directly to the battery voltage. 总共有六个调整器集成在Si4430/31/32中，除了数字调整器以外，所有调整器设计成仅采用内部退耦来工作，数字调整器需要一个外部1 µF退耦电容，所有调整器设计成采用+1.8~+3.6 V内部电源工作，PA的输出级内部不与调整器连接，直接与电池电压连接。 A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital regulator output. 电源电压应当仅与VDD脚连接，电压不应加在数字调整输出端。 6. Data Handling and Packet Handler 数据处理和数据包处理程序 The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the modem to operate with packet formats without a preamble or other legacy packet structures contact customer support. 内部调制解调器设计成用包含10101...报头结构的数据包形式工作，若要配置以不带报头的或其它传统数据包结构的数据包格式工作的调制解调器，请与客户支持部联系。 6.1. RX and TX FIFOs RX和TX堆栈 Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 17. \"Register 7Fh. FIFO Access\" is used to access both FIFOs. A burst write, as described in \"3.1. Serial Peripheral Interface (SPI)\" on page 18, to address 7Fh will write data to the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO. 两个64字节的堆栈集成在芯片中，如图17所示，一个用于RX，一个用于TX。\"寄存器7Fh. 堆栈访问\"用于访问两个堆栈。18页上的\"3.1.串行外设接口(SPI)\"中所描述的对地址7Fh的脉冲写将把数据写入TX堆栈中，从地址7Fh中的脉冲读将从RX堆栈中读出数据。 图17. 堆栈阈值 The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this register corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the contents of the TX FIFO. The second threshold for TX is the FIFO almost empty threshold, txaethr[5:0]. When the data being shifted out of the TX FIFO drops below the almost empty threshold an interrupt will be generated. The microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The transceiver can be configured so that when the TX FIFO is empty it will automatically exit the TX state and return to one of the low power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field (Reg 3Eh). When the packet ends, the chip will return to the state specified in register 07h. For example, if 08h is written to address 07h then the chip will return to the STANDBY state. If 09h is written then the chip will return to the READY state. TX堆栈有两个可编程阈值，当TX堆栈中的数据达到这些阈值时就发生一个中断事件，第一个阈值是堆栈几乎满阈值txafthr[5:0]，该寄存器中的值与字节数中的所需阈值相对应。当注入TX堆栈中的数据超过此阈值时，一个微控制器中断就产生，这样芯片可以进入发送方式以发送TX堆栈中的内容。TX的第二个阈值是堆栈几乎空txaethr[5:0]，当正在移出TX堆栈的数据跌落到几乎空以下时，中断将产生，微控制器将需要退出TX方式或者注入更多的数据到TX堆栈中。收发器可以配置成当TX堆栈为空时，它将自动退出TX状态并返回到低功率状态之一。当TX被开启时，它将发送在数据包长度字段(Reg 3Eh)中编程的字节数，当数据包结束时，芯片将返回至寄存器07h中规定的状态，譬如：如果08h被写入地址07h中，则芯片将返回至待机状态，如果09h被写入，则芯片将返回至准备状态。 Add R/W Function/ Description 功能/描述 R/W Operating & Function Control 2 操作功能控制2 R/W TX FIFO Control 1 TX堆栈控制1 R/W TX FIFO Control 2 TX堆栈控制2 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 00h 08 antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 7C Reserved 保留 Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h 7D Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. RX堆栈有一个称为堆栈几乎满阈值rxafthr[5:0]的可编程阈值，当输入的RX数据超过几乎满阈值时，将通过nIRQ引脚给微控制器产生一个中断，微控制器然后需要从RX FIFO中读出数据。 Add R/W Function/ Description 功能/描述 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 37h 7E R/W RX FIFO Control Reserved 保留 RX堆栈控制 Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be enabled by setting the Interrupt Enabled bits in \"Register 05h. Interrupt Enable 1\" and ―Register 06h. Interrupt Enable 2.‖ If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers. TX和RX堆栈可以采用ffclrtx和ffclrrx位来清零或复位，可以通过设置\"寄存器05h. 中断使能1\" 和―寄存器06h. 中断使能2‖来开启所有的中断，如果中断没有被开启，则该功能将不会在nIRQ引脚上产生中断，但中断状态寄存器中的位将仍然可以被正确读出。 6.2. Packet Configuration 数据包配置 When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. \"Register 30h. Data Access Control\" through ―Register 4Bh. Received Packet Length‖ control the configuration, status, and decoded RX packet data for Packet Handling. The usual fields for network communication (such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the Si4430/31/32 and reduces the required computational power of the microcontroller. 当使用堆栈时，对TX方式、RX方式或这两者可以开启自动数据包处理，\"寄存器30h. 数据访问控制\"到―寄存器4Bh.接收数据包长度‖控制数据包处理的配置、状态和解码的RX数据包数据。网络通信的通常字段(如：报头、同步字、标题、数据包长度和CRC)可以配置成自动加入数据有效载荷，产生数据包所需的字段通常很少改变，因此可以贮存在寄存器中。自动把这些字段加给数据有效载荷极大地减少了微控制器和Si4430/31/32之间的通信量，减小了微控制器所需的计算能力。 The general packet structure is shown in Figure 18. The length of each field is shown below the field. The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable lengths to accommodate different applications. The most common CRC polynominals are available for selection. 一般的数据包结构如图18中所示，每个字段的长度如下面的字段中所示，报头格式始终是以0开始的一系列的交替的1和0，所有字段具有可编程的长度以适应不同的应用，提供最常见的CRC多项式供选择。 图18 数据包结构 An overview of the packet handler configuration registers is shown in Table 13. 数据包处理程序配置寄存器概况如表格13中所示。 6.3. Packet Handler TX Mode 数据包处理程序TX方式 If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 19 provides an example transaction where the packet length is set to three bytes. 如果TX数据包长度被设置，则数据包处理程序将在返回至空闲方式之前发送数据包长度字段中的字节数并发出数据包已发送中断，若要恢复发送堆栈中的数据，则微控制器需要给芯片发送指 令以重新进入TX方式。图19提供了数据包长度设置为3字节的操作实例。 图19 在TX数据包处理程序中的多个数据包 6.4. Packet Handler RX Mode 数据包处理程序RX方式 6.4.1. Packet Handler Disabled 数据包处理程序关闭 When the packet handler is disabled certain fields in the received packet are still required. Proper modem operation requires preamble and sync when the FIFO is being used, as shown in Figure 20. Bits after sync will be treated as raw data with no qualification. This mode allows for the creation of a custom packet handler when the automatic qualification parameters are not sufficient. Manchester encoding is supported but data whitening, CRC, and header checks are not. 当数据包处理程序被关闭时，在收到的数据包中的某些字段仍然是需要的，当采用如图20中所示的堆栈时，正确的调制解调器操作需要报头和同步。在同步后的位将无条件地被当做原始数据，当自动限定参数不够时，此方式允许建立定制的数据包处理程序，曼彻斯特编码得到支持，但数据白化、CRC和报头校验不被支持。 图20 数据包处理程序关闭时所需的RX数据包结构 6.4.2. Packet Handler Enabled 数据包处理程序打开 When the packet handler is enabled, all the fields of the packet structure need to be configured. Register contents are used to construct the header field and length information encoded into the transmitted packet when transmitting. The receive FIFO can be configured to handle packets of fixed or variable length with or without a header. If multiple packets are desired to be stored in the FIFO, then there are options available for the different fields that will be stored into the FIFO. Figure 21 demonstrates the options and settings available when multiple packets are enabled. Figure 22 demonstrates the operation of fixed packet length and correct/incorrect packets. 当数据包处理程序被打开时，数据包结构的所有字段需要配置。寄存器内容用于构建发送时编码在发送数据包中的标题字段和长度信息，接收堆栈可以配置以处理带有或不带有标题的固定或可变长度的数据包，如果多个数据包需要贮存在堆栈中，那么可以提供针对贮存在堆栈中的不同字段的选项，图21表明了当开启多个数据包时可以提供的选项和设置，图22表明固定数据包长度的操作和正确/错误数据包。 图21 在RX数据包处理程序中的多个数据包 图22 在RX中带有CRC或报头错误的多个数据包 Table 13. Packet Handler Registers 表格13 数据包处理程序寄存器 Add R/W 30 31 32 33 34 35 Function/Description 功能/描述 D7 enpacrx 0 D6 lsbfrst rxcrc1 D5 crcdonly pksrch D4 skip2ph pkrx D3 enpactx pkvalid D2 encrc crcerror D1 crc[1] pktx D0 crc[0] pksent POR Def. 8Dh R/W Data Access Control 数据访问控制 R EzMAC status EzMAC状态 — 0Ch 22h 08h 2Ah R/W Header Control 1 标题控制1 R/W Header Control 2 标题控制2 R/W Preamble Length 报头长度 R/W Preamble Detection Control 报头检测控制 R/W Sync Word 3 同步字3 R/W Sync Word 2 同步字2 R/W Sync Word 1 同步字1 R/W Sync Word 0 同步字0 R/W Transmit Header 3 发送标题3 R/W Transmit Header 2 发送标题2 R/W Transmit Header 1 发送标题1 skipsyn bcen[3:0] hdlen[2] hdlen[1] hdlen[0] fixpklen hdch[3:0] synclen[1] synclen[0] prealen[8] prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] preath[4] preath[3] preath[2] preath[1] preath[0] rssi_off[2] rssi_off[1] rssi_off[0] 36 37 38 39 3A 3B 3C sync[31] sync[23] sync[15] sync[7] txhd[31] txhd[23] txhd[15] sync[30] sync[22] sync[14] sync[6] txhd[30] txhd[22] txhd[14] sync[29] sync[21] sync[13] sync[5] txhd[29] txhd[21] txhd[13] sync[28] sync[20] sync[12] sync[4] txhd[28] txhd[20] txhd[12] sync[27] sync[19] sync[11] sync[3] txhd[27] txhd[19] txhd[11] sync[26] sync[18] sync[10] sync[2] txhd[26] txhd[18] txhd[10] sync[25] sync[17] sync[9] sync[1] txhd[25] txhd[17] txhd[9] sync[24] sync[16] sync[8] sync[0] txhd[24] txhd[16] txhd[8] 2Dh D4h 00h 00h 00h 00h 00h 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B R/W Transmit Header 0 发送标题0 R/W Transmit Packet Length 发送数据包长度 R/W Check Header 3 校验标题3 R/W Check Header 2 校验标题2 R/W Check Header 1 校验标题1 R/W Check Header 0 校验标题1 R/W Header Enable 3 标题使能3 R/W Header Enable 2 标题使能2 R/W Header Enable 1 标题使能1 R/W Header Enable 0 标题使能0 R R R R R Received Header 3 收到标题3 Received Header 2 收到标题2 Received Header 1 收到标题1 Received Header 0 收到标题0 Received Packet Length 收到数据包长度 txhd[7] pklen[7] chhd[31] chhd[23] chhd[15] chhd[7] hden[31] hden[23] hden[15] hden[7] rxhd[31] rxhd[23] rxhd[15] rxhd[7] rxplen[7] txhd[6] pklen[6] chhd[30] chhd[22] chhd[14] chhd[6] hden[30] hden[22] hden[14] hden[6] rxhd[30] rxhd[22] rxhd[14] rxhd[6] rxplen[6] txhd[5] pklen[5] chhd[29] chhd[21] chhd[13] chhd[5] hden[29] hden[21] hden[13] hden[5] rxhd[29] rxhd[21] rxhd[13] rxhd[5] rxplen[5] txhd[4] pklen[4] chhd[28] chhd[20] chhd[12] chhd[4] hden[28] hden[20] hden[12] hden[4] rxhd[28] rxhd[20] rxhd[12] rxhd[4] rxplen[4] txhd[3] pklen[3] chhd[27] chhd[19] chhd[11] chhd[3] hden[27] hden[19] hden[11] hden[3] rxhd[27] rxhd[19] rxhd[11] rxhd[3] rxplen[3] txhd[2] pklen[2] chhd[26] chhd[18] chhd[10] chhd[2] hden[26] hden[18] hden[10] hden[2] rxhd[26] rxhd[18] rxhd[10] rxhd[2] rxplen[2] txhd[1] pklen[1] chhd[25] chhd[17] chhd[9] chhd[1] hden[25] hden[17] hden[9] hden[1] rxhd[25] rxhd[17] rxhd[9] rxhd[1] rxplen[1] txhd[0] pklen[0] chhd[24] chhd[16] chhd[8] chhd[0] hden[24] hden[16] hden[8] hden[0] rxhd[24] rxhd[16] rxhd[8] rxhd[0] rxplen[0] 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh — — — — — 6.5. Data Whitening, Manchester Encoding, and CRC 数据白化、曼彻斯特编码和CRC Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom sequence output from the built-in PN9 generator. The generator is initialized at the beginning of the payload. The receiver recovers the original data by repeating this operation. Manchester encoding can be used to ensure a dc-free transmission and good synchronization properties. When Manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to the nature of the encoding. The effective datarate when using Manchester encoding is limited to 128 kbps. The implementation of Manchester encoding is shown in Figure 24. Data whitening and Manchester encoding can be selected with \"Register 70h. Modulation Mode Control 1\". The CRC is configured via \"Register 30h. Data Access Control.\" Figure 23 demonstrates the portions of the packet which have Manchester encoding, data whitening, and CRC applied. CRC can be applied to only the data portion of the packet or to the data, packet length and header fields. Figure 24 provides an example of how the Manchester encoding is done and also the use of the Manchester invert (enmaniv) function. 数据白化可用于避免在发送的数据流中的0s或1s的扩展序列，以获得一个更均匀的频谱，当开启时，有效负载数据位与内置PN9发生器中的伪随机序列输出进行异或。该发生器在有效负载的开头进行初始化，接收器通过重复此操作恢复原来的数据。曼彻斯特编码可用于确保无直流的发送和好的同步特性，当采用曼彻斯特编码时，有效的数据速率是不变的，但实际的数据速率(报头长度等)由于编码性质而翻倍。当采用曼彻斯特编码时实际的数据速率限定在128 kbps，曼彻斯特编码的实现方式如图24中所示。数据白化和曼彻斯特编码可以采用\"寄存器70h. 调制方式控制1\"进行选择，CRC是通过\"寄存器30h. 数据访问控制\"配置的，图23表明了应用曼彻斯特编码、 数据白化和CRC的数据包部分。CRC仅适用于数据包的数据部分或数据、数据包长度和标题字段，图24提供了曼彻斯特编码如何执行以及采用曼彻斯特转换(enmaniv)函数的示例。 图23 数据白化、曼彻斯特编码和CRC操作 图24曼彻斯特编码示例 6.6. Preamble Detector 报头检测器 The Si4430/31/32 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in \"Register 33h. Header Control 2\" and \"Register 34h. Preamble Length\preamble detection threshold, preath[4:0] as set in \"Register 35h. Preamble Detection Control 1\preath[4:0]. Si4430/31/32具有一个集成的自动报头检测器，报头长度是利用―6.2.数据包配置‖中所描述的\"寄存器33h. 标题控制2\"和\"寄存器34h. 报头长度\"中的prealen[7:0]字段在1–256字节之间配置，在\"寄存器35h. 报头检测控制1\"中所设置的报头检测阈值以4位为单位，报头检测器搜索具有preath[4:0]长度的报头式样。 If a false preamble detect occurs, the receiver will continuing searching for the preamble when no sync word is detected. Once preamble is detected (false or real) then the part will then start searching for sync. If no sync occurs then a timeout will occur and the device will initiate search for preamble again. The timeout period is defined as the sync word length plus four bits and will start after a non-preamble pattern is recognized after a valid preamble detection. The preamble detector output may be programmed onto one of the GPIO or read in the interrupt status registers. 如果一个虚假的报头检测发生，则当检测不到同步字时接收器将继续搜索报头，一旦检测到报头(假的或真的)，此部分然后开始搜索同步，如果没有同步出现，则定时时间到将出现，此器件将开始再次搜索报头。定时时间长度被定义为同步字长度加4位，在有效报头检测后并且在一个非报头图案被识别后开始，报头检测器输出可以编程到一个GPIO中或者在中断状态寄存器中读出。 6.7. Preamble Length 报头长度 The preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the application. The required preamble length threshold will depend on when receive mode is entered in relation to the start of the transmitted packet and the length of the transmit preamble. With a shorter than recommended preamble detection threshold the probability of false detection is directly related to how long the receiver operates on noise before the transmit preamble is received. False detection on noise may cause the actual packet to be missed. The preamble detection threshold is programmed in register 35h. For most applications with a preamble length longer than 32 bits the default value of 20 is recommended for the preamble detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false detections may be tolerated. When antenna diversity is enabled a 20-bit preamble detection threshold is recommended. When the receiver is synchronously enabled just before the start of the packet, a shorter preamble detection threshold may be used. Table 14 demonstrates the recommended preamble detection threshold and preamble length for various modes. 报头检测阈值确定无线装置认定一个有效的报头必须接收到的有效报头位数，报头阈值应当根据应用性质调整。所需的报头长度阈值将取决于相对于发送数据包的开始和发送报头长度何时进入接收方式，当比推荐的报头检测阈值短时，虚假检测的概率与在收到发送报头之前接收器带噪声运行的时间长短直接有关。对噪声的虚假检测可能导致实际的数据包丢失，报头检测阈值在寄存器35h中编程，对于报头长度大于32位的大多数应用来说，20的默认值推荐用于报头检测阈值。如果可以容忍偶然的虚假检测，则可以选择更短的报头检测阈值。当分集式天线开启时，建议采用20位报头检测阈值。当在数据包开始前接收器被同步开启时，可以采用一个更短的报头检测阈值。表格14表明了针对各种方式的推荐的报头检测阈值和报头长度。 It is possible to use Si4432/31/30 in a raw mode without the requirement for a 101010 preamble. Contact customer support for further details. 可采用原始方式使用Si4432/31/30而无需101010报头，关于进一步的详情，请与客户支持部联系。 Table 14. Minimum Receiver Settling Time 表格14 接收器最小稳定时间 Approximate Receiver Settling Time 接收器的大致稳定时间 1 byte 字节 2 byte 1 byte 2 byte 2 byte 8 byte Recommended Preamble Length with 8-Bit Detection Threshold 采用8位检测阈值的推荐的报头长度 20 bits 位 28 bits — — 3 byte — Recommended Preamble Length with 20-Bit Detection Threshold 采用20位检测阈值的推荐的报头长度 32 bits 40 bits 64 bits 8 byte 4 byte 8 byte Mode 方式 (G)FSK AFC Disabled FSK AFC关闭 (G)FSK AFC Enabled FSK AFC开启 (G)FSK AFC Disabled +Antenna Diversity Enabled FSK AFC关闭+分集式天线开启 (G)FSK AFC Enabled +Antenna Diversity Enabled FSK AFC开启+分集式天线开启 OOK 开关键控 OOK + Antenna Diversity Enabled 开关键控+分集式天线开启 Note: The recommended preamble length and preamble detection threshold listed above are to achieve 0% PER. They may be shortened when occasional packet errors are tolerable. 注释：上述推荐的报头长度和报头检测阈值将以0% PER(位误码率)实现, 当可以容忍偶然的数据包错误时, 它们可以缩短。 6.8. Invalid Preamble Detector 无效报头检测器 When scanning channels in a frequency hopping system it is desirable to determine if a channel is valid in the minimum amount of time. The preamble detector can output an invalid preamble detect signal. which can be used to identify the channel as invalid. After a configurable time set in Register 60h[7:4], an invalid preamble detect signal is asserted indicating an invalid channel. The period for evaluating the signal for invalid preamble is defined as (inv_pre_th[3:0] x 4) x Bit Rate Period. The preamble detect and invalid preamble detect signals are available in \"Register 03h. Interrupt/Status 1\" and ―Register 04h. Interrupt/Status 2.‖ 当在跳频系统中扫描信道时，需要在最短时间内确定信道是否有效，报头检测器能够输出一个无效的报头检测信号用于确定该信道无效。在寄存器60h[7:4]中设置的可配置时间后，一个无效的报头检测信号将发出表明一个无效信道，评价无效报头信号的时间被定义为(inv_pre_th[3:0] x 4) x位速率时间，报头检测和无效报头检测信号在\"寄存器03h. 中断/状态 1\" 和 ―寄存器 04h. 中断/状态 2‖中提供。 6.9. Synchronization Word Configuration 同步字配置 The synchronization word length for both TX and RX can be configured in Reg 33h, synclen[1:0]. The expected or transmitted sync word can be configured from 1 to 4 bytes as defined below: TX和RX的同步字长度可以在寄存器33h, synclen[1:0]中配置，期待的或发送的同步字可以按照以下规定在1~4之间配置： synclen[1:0] = 00—Expected/Transmitted Synchronization Word (sync word) 3. synclen[1:0] = 00—期待的/发送的同步字(sync word) 3. synclen[1:0] = 01—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2. synclen[1:0] = 01—期待的/发送的同步字3 在前, 后面跟着同步字2. synclen[1:0] = 10—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2, followed by sync word 1. synclen[1:0] = 10—期待的/发送的同步字3 在前, 后面跟着同步字2, 跟着同步字1. synclen[1:0] = 11—Send/Expect Synchronization Word 3 first, followed by sync word 2, followed by sync word 1,followed by sync word 0. synclen[1:0] = 11—期待的/发送的同步字3 在前, 后面跟着同步字2, 跟着同步字1, 跟着同步字0. The sync is transmitted or expected in the following sequence: sync 3sync 2sync 1sync 0. The sync word values can be programmed in Registers 36h–39h. After preamble detection, the part will search for sync for a fixed period of time. If a sync is not recognized in this period, a timeout will occur, and the search for preamble will be reinitiated. 同步字发送按照下列顺序: sync 3sync 2sync 1sync 0，同步字值可以在寄存器36h–39h中编程，在报头检测后，器件将搜索同步字一个固定时间，如果在该时间内没有确认一个同步，则定时时间到将发生，报头搜索将重新启动。 The timeout period after preamble detections is defined as the value programmed into the sync word length plus four additional bits. 在报头检测后的定时时间定义为编程在同步字长度+4个附加位中的值。 6.10. Receive Header Check 接收标题检查 The header check is designed to support 1–4 bytes and broadcast headers. The header length needs to be set in register 33h, hdlen[2:0]. The headers to be checked need to be set in register 32h, hdch[3:0]. For instance, there can be four bytes of header in the packet structure but only one byte of the header is set to be checked (i.e., header 3). For the headers that are set to be checked, the expected value of the header should be programmed in chhd[31:0] in Registers 3F–42. The individual bits within the selected bytes to be checked can be enabled or disabled with the header enables, hden[31:0] in Registers 43–46. For example, if you want to check all bits in header 3 then hden[31:24] should be set to FF but if only the last 4 bits are desired to be checked then it should be set to 00001111 (0F). Broadcast headers can also be programmed by setting bcen[3:0] in Register 32h. For broadcast header check the value may be either ―FFh‖ or the value stored in the Check Header register. A logic equivalent of the header check for Header 3 is shown in Figure 25. A similar logic check will be done for Header 2, Header 1, and Header 0 if enabled. 标题检查设计成支持1-4字节和传送标题，标题长度需要在寄存器33h, hdlen[2:0]中设置，待检查的标题需要在寄存器32h, hdch[3:0]中设置。例如：在数据包结构中可以有4字节标题，但仅有一字节的标题被设置为检查(亦即标题3)。对于设置为待检查的标题，标题的期望值应当在寄存器3F–42的chhd[31:0]中进行编程。在寄存器43–46的hden[31:0]标题开启时，在待检查的选择字节内的单个位可以开启或关闭。譬如：如果你想检查标题3中的所有位，那么hden[31:24]应当设置为FF，但如果只需要检查最后4位，那么它应当设置为00001111 (0F)。传送标题也可以通过设置寄存器32h中的bcen[3:0]进行编程。标题3的标题检查的逻辑等式如图25中所示，如果它们开启的话，则可以对标题2、标题1和标题0进行类似的逻辑检查。 图25 标题 6.11. TX Retransmission and Auto TX TX重复传输和自动传输 The Si4430/31/32 is capable of automatically retransmitting the last packet loaded in the TX FIFO. Automatic retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature is useful for beacon transmission or when retransmission is required due to the absence of a valid acknowledgement. Only packets that fit completely in the TX FIFO can be automatically retransmitted. Si4430/31/32能够自动重复传输在TX堆栈中装载的最后的数据包，进入TX状态用txon位可以设置自动重复传输，无需重新装载TX堆栈，此特性对于信标传输或者当由于无有效的应答而需要重新传输时很有用，只有完全适合于TX堆栈的数据包能够被自动重复传输。 An automatic transmission function is available, allowing the radio to automatically start or stop a transmission depending on the amount of data in the TX FIFO. 自动传输功能是可以使用的，使得无线装置根据TX堆栈中的数据量自动开始或停止传送。 When autotx is set in ―Register 08. Operating & Function Control 2\automatically enter the TX state when the TX FIFO almost full threshold is exceeded. Packets will be transmitted according to the configured packet length. To stop transmitting, clear the packet sent or TX FIFO almost empty interrupts must be cleared by reading register. 当在―寄存器08. 操作和功能控制2\"中的autotx被置位时，并且当超过TX堆栈几乎满阈值时，收发器将自动进入TX状态，数据包将根据配置的数据包长度传输，若要停止传输，则对数据包已发送或TX堆栈几乎空中断清除必须通过读寄存器而被清除。 7. RX Modem Configuration 接收调制解调器配置 A Microsoft Excel (WDS) parameter calculator or Wireless Development Suite (WDS) calculator is provided to determine the proper settings for the modem. The calculator can be found on www.silabs.com or on the CD provided with the demo kits. An application note is available to describe how to use the calculator and to provide advanced descriptions of the modem settings and calculations. 提供了一个微软Excel (WDS)参数计算器或无线开发套件(WDS)计算器来确定调制解调器的正确设置，该计算器可以在www.silabs.com网址或带有演示套件的CD中提供。可以提供应用说明描述如何使用此计算器并且提供关于调制解调器设置和计算的最新说明。 7.1. Modem Settings for FSK and GFSK 调制解调器的FSK和GFSK设置 The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 2.6 to 620 kHz. The receiver data-rate, modulation index, and bandwidth are set via registers 1C–25h. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb). 调制解调器在数字域中进行信道选择和解调，信道滤波带宽可以在2.6~620 kHz范围内配置，接收器数据速率、调制指数和带宽是通过寄存器1C–25h设置的，调制指数等于峰值偏差除以数据速率(Rb)的2倍。 When Manchester coding is disabled, the required channel filter bandwidth is calculated as BW = 2Fd + Rb where Fd is the frequency deviation and Rb is the data rate. 当曼彻斯特编码被关闭时，所需的信道带宽是按BW = 2Fd + Rb公式计算的，此处Fd为频偏，Rb为数据速率。 8. Auxiliary Functions 辅助功能 8.1. Smart Reset 智能复位 The Si4430/31/32 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur: Si4430/31/32包含一个集成在内的增强的智能复位或POR(上电复位)电路，POR电路包含一个典型的阈值复位和斜率检测上电复位电路，此复位电路设计成能够在任何情况下产生可靠的复位信号，在下列条件发生时，复位将产生： Initial power on, VDD starts from gnd: reset is active till VDD reaches VRR (see table); When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR; A software reset via ―Register 08h. Operating Mode and Function Control 2‖: reset is active for time TSWRST On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit: 初始上电，VDD从gnd开始: 复位在进行直至VDD达到VRR (参看表格); 当由于某种原因VDD减小至低于VLD: 复位在进行直至VDD达到VRR; 通过―寄存器08h. 操作方式和功能控制2‖: 复位进行TSWRST时间 当电源电压超过下列功能受限的时间时, 在VDD脉冲的上升沿: 图26 POR脉冲参数 Table 15. POR Parameters Parameter 参数 Release Reset Voltage 释放复位电压 Power-On VDD Slope 上电VDD斜率 Low VDD Limit VDD下限 Software Reset Pulse 软件复位脉冲 Threshold Voltage 阈值电压 Reference Slope 基准斜率 VDD Glitch Reset Pulse VDD复位脉冲 Symbol 符号 VRR SVDD VLD TSWRST VTSD k TP tested VDD slope region 测试VDD斜坡区域 VLD reset signal is available by default on GPIO_1. 复位将把所有寄存器复位至它们的默认值，复位信号也用做输出，通过采用GPIO_0的默认设置为微控制器所使用，反相的复位信号一般在GPIO_1上提供。 8.2. Microcontroller Clock 微控制器时钟 The 30 MHz crystal oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default setting for GPIO2 is to output the microcontroller clock signal with a frequency of 1 MHz. 30 MHz晶体振荡器频率被内部分频并且可以通过GPIO2输出至微控制器，该特性对于降低材料成本很有用，在系统中仅使用一个晶体。系统时钟频率可以按照如下方式在八个选项中选择，除了32.768 kHz选项外，其它所有频率都是通过对晶振频率分频获得的，32.768 kHz时钟信号是从内部RC振荡器或外部32 kHz晶体获得的，GPIO2的默认设置是输出1 MHz频率的微控制器时钟信号。 Add 0A mclk[2:0] 000 001 010 011 100 101 110 111 Clock Frequency 时钟频率 30 MHz 15 MHz 10 MHz 4 MHz 3 MHz 2 MHz 1 MHz 32.768 kHz R/W R/W Function/Description 功能/描述 Microcontroller Output Clock 微控制器输出时钟 D7 D6 D5 clkt[1] D4 clkt[0] D3 enlfc D2 mclk[2] D1 mclk[1] D0 mclk[0] POR Def. 06h If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller while the Si4430/31/32 is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in ―Register 0Ah. Microcontroller Output Clock.\" When enlfc = 1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the system clock in all IDLE, TX, or RX states. When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kHz from the RC oscillator or 32.768 XTAL. 当Si4430/31/32处于睡眠方式时，如果微控制器时钟选项正在使用，则微控制器可能需要一个系统时钟，因为晶体振荡器在睡眠方式被关闭以节省电流，低功率的32.768 kHz时钟可以被自动 切换成为微控制器时钟。该特性叫做低频时钟开启，可以通过―寄存器0Ah. 微控制器输出时钟\"的enlfc位开启。当enlfc = 1时，芯片处于睡眠方式，此时将给微控制器提供32.768 kHz时钟作为系统时钟，而不管mclk[2:0]的设置。例如：如果mclk[2:0] = 000, 则在空闲、发送或接收状态30 MHz将通过GPIO输出脚提供给微控制器作为系统时钟，当芯片进入睡眠方式时，系统时钟将自动切换至来自RC振荡器32.768 XTAL的32.768 kHz。 Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in ―Register 0Ah. Microcontroller Output Clock.\" If the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the system clock signal. Setting the clkt[1:0] field will provide additional cycles of the system clock before it shuts off. 微控制器时钟的另一个有用的特性是时钟跟踪，在―寄存器0Ah.微控制器输出时钟\"中的clkt[1:0]，如果低频时钟特性没有开启(enlfc = 0), 那么在睡眠方式微控制器的系统时钟就被关闭，但是，在系统时钟信号关机之前，它对于给微控制器完成其操作提供几个额外周期可能是有用的，设置clkt[1:0]字段将在系统时钟关闭前提供额外的周期。 clkt[1:0] 00 01 10 11 Clock Tail 时钟跟踪 0 cycles 0个周期 128 cycles 128个周期 256 cycles 256个周期 512 cycles 512个周期 If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption will not be achieved until the interrupt is read. For instance, if the chip is commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the interrupt has been cleared. 如果中断被触发，则微控制器时钟将保持开启，而不管所选择的方式，一旦中断被读，机器状态将移至选择的方式。在中断被读之前，最小电流消耗将达不到，例如：如果芯片被命令进入睡眠方式，但中断已经发生，则30 MHz XTAL在中断被清除之前不会被关闭。 8.3. General Purpose ADC 通用模数转换器 An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. Registers 0Fh \"ADC Configuration\\"Amplifier Offset\" can be used to configure the ADC operation. Details of these registers are in ―AN440: EZRadioPRO Detailed Register Descriptions.‖ 一个八位SAR ADC集成在内作为一般用途，也用做使得片上温度传感器读数数字化，寄存器0Fh \"ADC 配置\传感器偏置\" 和4Fh \"放大器偏置\"可用于配置ADC操作，这些寄存器的详细说明中―AN440: EZRadioPRO寄存器详细说明‖中。 Every time an ADC conversion is desired, bit 7 \"adcstart/adcbusy\" in Register 1Fh ―Clock Recovery Gearshift Override‖ must be set to 1. This is a self clearing bit that will be reset to 0 at the end of the conversion cycle of the ADC. The conversion time for the ADC is 350 µs. After this time or when the \"adcstart/adcbusy\" bit is cleared, then the ADC value may be read out of ―Register 11h. ADC Value.\" 每当需要ADC转换时，寄存器1Fh ―时钟恢复移位覆盖‖中的位7 \"adcstart/adcbusy\"必须设置为1，这是一个自动清零位，在ADC转换周期结束时将复位至0。ADC的转换时间为350 µs，在该时间后或者当\"adcstart/adcbusy\"位被清零时，ADC的值可以从―寄存器11h. ADC值\"中读出。 The architecture of the ADC is shown in Figure 27. The signal and reference inputs of the ADC are selected by adcsel[2:0] and adcref[1:0] in register 0Fh ―ADC Configuration‖, respectively. The default setting is to read out the temperature sensor using the bandgap voltage (VBG) as reference. With the VBG reference the input range of the ADC is from 0-1.02 V with an LSB resolution of 4 mV (1.02/255). Changing the ADC reference will change the LSB resolution accordingly. ADC的结构如图27中所示，ADC的信号和基准输入分别由寄存器0Fh ―ADC配置‖中的adcsel[2:0] 和adcref[1:0]位选择。默认设置是利用带隙电压(VBG)作为基准来读出温度传感器。采用VBG基准时，ADC的输入范围为0-1.02 V，LSB分辨率为4 mV (1.02/255)，改变ADC基准将相应地改变LSB分辨率。 A differential multiplexer and amplifier are provided for interfacing external bridge sensors. The gain of the amplifier is selectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage (VDD) dependent gain and offset. The reference voltage of the ADC can be changed to either VDD/2 or VDD/3. A programmable VDD dependent offset voltage can be added using soffs[3:0] in register 10h. 差分多路器和放大器用做与外部传感器桥路连接，放大器的增益由寄存器0Fh中的adcgain[1:0]选择，大多数传感器桥路具有与增益和偏置有关的电源电压(VDD)，ADC的基准电压可以改成VDD/2 或VDD/3，可编程的与VDD有关的偏置电压可以利用寄存器10h中的soffs[3:0]增加。 See ―AN448: General Purpose ADC Configuration‖ for more details on the usage of the general purpose ADC. 关于通用ADC的用法的更多细节，请参看―AN448: 通用 ADC配置‖。 图27 通用ADC结构 Add R/W 0F 10 11 R/W R/W R Function/Description 功能/描述 ADC Configuration ADC配置 Sensor Offset 传感器偏置 ADC Value ADC值 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 00h 00h adcstart/adcbusy adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] adc[7] adc[6] adc[5] adc[4] soffs[3] adc[3] soffs[2] adc[2] soffs[1] adc[1] soffs[0] adc[0] — 8.4. Temperature Sensor 温度传感器 An integrated on-chip analog temperature sensor is available. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through \"Register 10h. ADC Sensor Amplifier Offset.\" The range of the temperature sensor is configurable. Table 16 lists the settings for the different temperature ranges and performance. 集成的片上模拟温度传感器可供使用，当温度传感器被选择为ADC的输入或者当在模拟测试总线上选择了模拟温度电压时，此温度传感器可利用通用ADC进行数字转换并通过\"寄存器10h. ADC传感器放大器偏置\"从SPI读出。温度传感器的范围是可以配置的，表格16列具了不同温度范围和性能的设置。 To use the Temp Sensor: 使用温度传感器 1. Set the input for ADC to the temperature sensor, \"Register 0Fh. ADC Configuration\"—adcsel[2:0] = 000 2. Set the reference for ADC, \"Register 0Fh. ADC Configuration\"—adcref[1:0] = 00 3. Set the temperature range for ADC, \"Register 12h. Temperature Sensor Calibration\"—tsrange[1:0] 4. Set entsoffs = 1, \"Register 12h. Temperature Sensor Calibration\" 5. Trigger ADC reading, \"Register 0Fh. ADC Configuration\"—adcstart = 1 6. Read temperature value—Read contents of \"Register 11h. ADC Value\" 1. 设置ADC至温度传感器的输入，\"寄存器 0Fh. ADC配置\"—adcsel[2:0] = 000 2. 设置ADC基准，\"寄存器0Fh. ADC配置\"—adcref[1:0] = 00 3. 设置ADC的温度范围，\"寄存器12h. 温度传感器校正\"—tsrange[1:0] 4. 设置entsoffs = 1, \"寄存器12h. 温度传感器校正\" 5. 触发ADC读数, \"寄存器0Fh. ADC 配置\"—adcstart = 1 6. 读温度值—读\"寄存器11h. ADC 值\"的内容 Add 12 R/W R/W Function/Description 功能/描述 Temperature Sensor Control 温度传感器控制 Temperature Value Offset 温度值偏置 POR Def. tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] vbgtrim[1] vbgtrim[0] 20h D7 D6 D5 D4 D3 D2 D1 D0 13 R/W tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h Table 16. Temperature Sensor Range 表格16 温度传感器范围 entoff 1 1 1 1 0* tsrange[1] 0 0 1 1 1 tsrange[0] 0 1 0 1 0 Temp. range 温度范围 –64 … 64 –64 … 192 0 … 128 –40 … 216 0 … 341 Unit 单位 °C °C °C °F °K Slope 斜率 8 mV/°C 4 mV/°C 8 mV/°C 4 mV/°F 3 mV/°K ADC8 LSB 0.5 °C 1 °C 0.5 °C 1 °F 1.333 °K *Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of EN_TOFF is 1. *注释: 绝对温度方式, 无温度偏移, 此方式仅用于测试, EN_TOFF的POR值为1. The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 °C calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in ―Register 12h. Temperature Sensor Control‖ and setting the offset with the tvoffs[7:0] bits in ―Register 13h. Temperature Value Offset.‖ This method adds a positive offset digitally to the ADC value that is read in ―Register 11h. ADC Value.‖ The other method of calibration is to use the tstrim which compensates the analog circuit. This is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in ―Register 12h. Temperature Sensor Control.‖ 温度传感器的斜率线性很好并且是单调的, 对于高于10 °C的绝对精度, 校正是必需的, 温度传感器可以通过设置―寄存器12h. 温度传感器控制‖中的entsoffs = 1以及用―寄存器13h. 温度值偏置‖中的tvoffs[7:0]位设置偏置来进行校正. 此方法给在―寄存器11h. ADC值‖中读出的ADC值以数字方式增加一个正偏置, 另一个校正方法是采用补偿模拟电路的tstrim, 这可以通过设置entstrim = 1并采用―寄存器12h. 温度传感器控制‖中的tstrim[2:0]位补偿温度。 With this method of calibration, a negative offset may be achieved. With both methods of calibration better than ±3 °C absolute accuracy may be achieved. 当采用此校正方法时，可以获得一个负偏置，采用这两种校正方法，可以获得高于±3 °C的绝对精度。 The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 28. The value of the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature in Temp Range. 温度传感器和ADC8的不同范围如图28中所示，ADC8的值可以通过ADC8Value x ADC8 LSB +温度范围中最低温度转换成温度读数。 For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64. 例如：对于tsrange = 00, 则Temp = ADC8Value x 0.5 – 64。 图28 采用ADC8的温度范围 8.5. Low Battery Detector 低电池检测器 A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in \"Register 1Ah. Low Battery Detector Threshold.\" When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can confirm source of the interrupt by reading \"Register 03h. Interrupt/Status 1\" and ―Register 04h. Interrupt/Status 2.‖ 具有数字读数的低电池检测器(LBD)集成在此芯片中，数字阈值可以编程到\"寄存器1Ah. 低电池检测阈值\"的lbdt[4:0]字段中，当数字的电池电压达到此阈值时，将在微控制器的nIRQ脚上产生一个中断，微控制器通过读\"寄存器03h. 中断/状态 1\"和―寄存器 04h. 中断/状态 2‖来确定中断源。 If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable the RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through \"Register 1Bh. Battery Voltage Level\" at any time when the LBD is enabled. The low battery detect function is enabled by setting enlbd=1 in \"Register 07h. Operating Mode and Function Control 1\". 如果当芯片处于睡眠方式时LBD被开启，则它将自动开启RC振荡器，该振荡器将定时打开 LBD电路来测量电池电压。当LBD被开启时，电池电压也可以通过\"寄存器1Bh. 电池电压大小\"在任何时候读出，低电池检测功能可以通过设置\"寄存器07h. 操作方式和功能控制1\" enlbd=1来开启。 Ad 1A 1B Function/Description 功能/描述 Low Battery Detector Threshold R/W 低电池检测阈值 Battery Voltage Level R 电池电压大小 R/W D7 0 0 D6 0 D5 D4 lbdt[4] vbat[4] D3 lbdt[3] vbat[3] D2 lbdt[2] vbat[2] D1 lbdt[1] vbat[1] D0 lbdt[0] vbat[0] POR Def. 14h — The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled (enlbd = 1 in \"Register 07h.Operating Mode and Function Control 1\") the battery voltage may be read at anytime by reading \"Register 1Bh.Battery Voltage Level.\" A battery voltage threshold may be programmed in ―Register 1Ah. Low Battery Detector Threshold.\" When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in ―Register 06h. Interrupt Enable 2.‖ The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. LBD输出可以通过5位ADC被数字化，当LBD功能被开启(\"寄存器07h. 操作方式和功能控制1\" 中的enlbd=1)时，电池电压可以通过读\"寄存器1Bh. 电池电压大小\"在任何时候读出。电池电压阈值可以在―寄存器1Ah.低电池检测阈值\"中进行编程，如果―寄存器06h. 中断使能2‖中的LBD中断被开启，则当电池电压下降至低于电池电压阈值时，在微控制器nIRQ引脚上将产生一个中断，微控制器然后将需要通过读中断状态寄存器地址03和04h来确认中断。 The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 µs to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required. LBD ADC的LSB(最低有效位)的步幅为50 mV，ADC的范围如下表中所示。如果LBD被开启，则LBD和ADC将每隔1秒被自动开启约250 µs以测量电压，这使得传感器方式的电流消耗被减小至最低，在中断被激活前，需要4次连续读数。 ADC Value ADC值 0 1 2 … 29 30 31 VDD Voltage VDD电压 [V] < 1.7 1.7–1.75 1.75–1.8 … 3.1–3.15 3.15–3.2 > 3.2 8.6. Wake-Up Timer and 32 kHz Clock Source 唤醒定时器和32 kHz时钟源 The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. 芯片包含一个可用来从睡眠方式定时唤醒芯片的集成的唤醒定时器。 The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in \"Register 07h. Operating Mode and Function Control 1\" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14–16h, \"Wake Up Timer Period.\" At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Registers 03h–04h, \"Interrupt Status 1 & 2\". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h–18h. 唤醒定时器依靠内部32.768 kHz RC振荡器运行，当处于睡眠方式时，唤醒定时器可以配置为运行。如果当进入睡眠方式时\"寄存器07h. 操作方式和功能控制1\"中的enwt = 1，则唤醒定时器将计时寄存器14–16h, \"唤醒定时器时长\"中所规定的时间，如果中断被开启，则在该时长结束时，在nIRQ引脚上将产生一个中断。微控制器然后将需要通过读寄存器03–04h\"中断状态1 & 2\"来确认中断，唤醒定时器值可以在任何时候通过只读寄存器17h–18h的wtv[15:0]被读出。 The formula for calculating the Wake-Up Period is the following: 计算唤醒周期的公式如下： WUT Register WUT寄存器 wtr[4:0] wtm[15:0] Description 说明 R Value in Formula 公式中的R值 M Value in Formula 公式中的M值 Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by using the R value. 如果需要获得比采用R值所能得到的更高分辨率，则公式中D变量的使用才有必要 Add 14 Function/Description 功能/描述 Wake-Up Timer Period 1 R/W 唤醒定时器周期1 R/W D7 D6 D5 D4 wtr[4] D3 wtr[3] D2 wtr[2] D1 wtr[1] D0 wtr[0] POR Def. 03h 15 16 17 18 Wake-Up Timer Period 2 唤醒定时器周期2 Wake-Up Timer Period 3 R/W 唤醒定时器周期3 Wake-Up Timer Value 1 R 唤醒定时器值1 Wake-Up Timer Value 2 R 唤醒定时器值2 R/W wtm[15] wtm[7] wtv[15] wtv[7] wtm[14] wtm[6] wtv[14] wtv[6] wtm[13] wtm[5] wtv[13] wtv[5] wtm[12] wtm[4] wtv[12] wtv[4] wtm[11] wtm[3] wtv[11] wtv[3] wtm[10] wtm[2] wtv[10] wtv[2] wtm[9] wtm[1] wtv[9] wtv[1] wtm[8] wtm[0] wtv[8] wtv[0] 00h 00h — — There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in ―Register 06h. Interrupt Enable 2.‖ If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 29. 采用唤醒定时器(WUT)有两种不同的方式，这取决于―寄存器06h. 中断使能2.‖中的WUT中断是否被开启，如果WUT中断被开启，则当定时时间到时，nIRQ引脚将变为低。芯片也会改变状态，这样30 MHz XTAL就开启，微控制器时钟输出也可给微控制器用来处理中断，另一个用法是不开启WUT中断而使用WUT GPIO设置。在这一操作方式，芯片将不改变状态直至得到微控制器的指令。WUT操作的不同方式和电流消耗影响如图29中所示。 A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h \"Operating & Function Control 1\external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set,all internal functions such as WUT, micro-controller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator. 为了更好的定时精度，可以采用一个32 kHz XTAL，通过设置寄存器07h \"操作和功能控制1\"中的x32 ksel位，GPIO0进行自动配置使得一个外部的32 kHz晶体可与此引脚连接。在此方式，GPIO0对寄生电容很敏感，因此，XTAL物理位置应当尽量靠近此引脚，一旦x32 ksel位被置位，则所有内部功能如：WUT、微控制器时钟、LDC方式将使用32 kHz晶体而不使用32 kHz RC振荡器。 图29 WUT中断和WUT操作 8.7. Low Duty Cycle Mode 低占空比方式 The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. 低占空比方式可用于自动唤醒接收器以检查是否提供了有效信号。 The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R value (―Register 14h. Wake-up Timer Period 1‖) is shared between the WUT and the TLDC. The ldc[7:0] bits are located in ―Register 19h. Low Duty Cycle Mode Duration.‖ The time of the TLDC is determined by the formula below: 低占空比方式的基本操作如下图中所示，如果没有检测到一个有效的报头或同步字，则芯片将返回至睡眠方式直至一个新的WUT周期开始。如果检测到一个有效的报头或同步字，则在此阶段接收器将按照低占空比方式时长(TLDC)进行扩展以接收所有的数据包，WUT周期必须结合低占空比方式时长一起进行设置，R值(―寄存器14h. 唤醒定时周期1‖)在WUT和TLDC之间共享，ldc[7:0]位在―寄存器19h. 低占空比方式时长‖中，TLDC的时间由下式确定： 图30 低占空比方式 8.8. GPIO Configuration GPIO配置 Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control,Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. 提供了三个通用的IOs (GPIOs)，许多功能如：特殊中断、TRSW控制、微控制器输出等可以按传送至下表中所示的GPIO引脚，当处于关机方式时，所有的GPIO焊盘被拉低。 Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess current consumption. 注意：在待机或睡眠方式，ADC不应选择为GPIO的输入，否则会引起太大的电流消耗。 Add R/W Function/Description 功能/描述 GPIO0 Configuration GPIO0配置 GPIO1 Configuration GPIO1配置 GPIO2 Configuration GPIO2配置 I/O Port Configuration I/O端口配置 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 00h 0B R/W gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 0C R/W gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0D R/W gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0E R/W extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO1和GPIO2的GPIO设置与GPIO0的设置一样，除了00000默认设置以外，每个GPIO的默认设置如下表中所示： GPIO GPIO0 GPIO1 GPIO2 00000—Default Setting 默认设置 POR POR Inverted POR反相 Microcontroller Clock 微控制器时钟 For a complete list of the available GPIO's see ―AN440: EZRadioPRO Detailed Register Descriptions‖. 关于可以提供的GPIO的完整列表，请参看―AN440: EZRadioPRO详细的寄存器说明‖。 The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions. GPIO驱动强度可以用gpioXdrv[1:0]位进行调整，设置较高的值将通过改变驱动器规格来增加驱动强度和GPIO电流提供能力。当采用微控制器时钟时，需要对设置驱动强度和装载GPIO2特别注意，过度装载或不适当的驱动可能导致寄生发射增多。 8.9. Antenna Diversity 分集式天线 To mitigate the problem of frequency-selective fading due to multi-path propagation, some transceiver systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an external SPDT RF switch (such as PIN diode or GaAs switch) are available on the GPIOx pins. The operation of these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The antdiv[2:0] bits are found in register 08h ―Operating & Function Control 2.‖ 为了抑制由于多通道传输造成的频率选择性衰减，一些收发器采用称之为分集式天线方案，在该方案中，采用两根天线。每当收发器进入RX方式，就评价每根天线的接收信号强度，此评价过程在数据包的报头期间发生，具有最强接收信号强度的天线然后用于其余的RX数据包，同一天线也将用于下一个相应的TX数据包。此芯片采用集成的分集式天线控制算法完全支持分集式天线，控制外部的SPDT RF开关(例如：PIN二极管或GaAs开关)所需的信号在GPIOx脚上提供，这些GPIO信号的运行是可编程的，可以采用不同的分集式天线结构和配置，antdiv[2:0]位可以在寄存器08h ―操作和功能控制2‖中找到。 The GPIO pins are capable of sourcing up to 5 mA of current, so it may be used directly to forward-bias a PIN diode if desired. GPIO引脚可以输出最大5 mA的电流，因此在需要时它可直接用于正向偏置的PIN二极管。 The antenna diversity algorithm will automatically toggle back and forth between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna selection is 8 bytes. A special antenna diversity algorithm (antdiv[2:0] = 110 or 111) is included that allows for shorter preamble lengths for beacon mode in TDMA-like systems where the arrival of the packet is synchronous to the receiver enable. The recommended preamble length to obtain optimal antenna selection for synchronous mode is 4 bytes. 分集式天线算法将在天线之间来回自动翻转直至数据包开启到达，最佳天线选择的推荐的报头长度为8位，配备一种特殊的分集式天线算法(antdiv[2:0] = 110或111)，它允许在数据包到达与接收器使能同步的TDMA之类系统中给信标提供更短的报头长度，获得同步方式的最佳天线选择的推荐的报头长度为4个字节。 Add 08 R/W Function/Description 功能/描述 D7 antdiv[2] D6 antdiv[1] D5 antdiv[0] D4 rxmpk D3 D2 D1 ffclrrx D0 ffclrtx POR Def. 00h R/W Operating & Function Control 2 操作和功能控制2 autotx enldm Table 17. Antenna Diversity Control 表格17 分集式天线控制 antdiv[2:0] RX/TX State 接收/发送状态 GPIO Ant1 000 001 010 0 1 0 GPIO Ant2 1 0 1 Non RX/TX State 非接收/发送状态 GPIO Ant1 0 0 1 GPIO Ant2 0 0 1 011 100 101 110 111 1 Antenna Diversity Algorithm 分集式天线算法 Antenna Diversity Algorithm 分集式天线算法 0 1 0 1 0 1 1 0 1 0 1 Antenna Diversity Algorithm in Beacon Mode 信标方式下的分集式天线算法 Antenna Diversity Algorithm in Beacon Mode 信标方式下的分集式天线算法 8.10. RSSI and Clear Channel Assessment RSSI和清晰信道评估 Received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 31 demonstrates the relationship between input power level and RSSI value. The absolute value of the RSSI will change slightly depending on the modem settings. The RSSI may be read at anytime, but an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the following options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA). 接收信号强度指示(RSSI)是正在调谐的信道中信号强度，RSSI值可以从一个每位0.5 dB分辨率的 8位寄存器中读出，图31表明了输入功率电平和RSSI值之间的关系。RSSI的绝对值将随着调制解调器的设置不同而稍微变化。RSSI可以在任何时候读出，但可能偶然出现差错。如果在更新期间读出，则RSSI值可能是错的。更新周期为每隔4 Tb约10 ns，对于10 kbps速率，这会造成RSSI可能被读错的概率为1/40,000，这种概率很低，但为了避免它，建议采用下列选项之一： 大数轮询、在RSSI中断的1 Tb内读出RSSI值或者利用在清晰信道评估(CCA)的下一节中所描述的RSSI阈值。 Add 26 27 Function/Description 功能/描述 Received Signal Strength R Indicator 接收信号强度指示 RSSI Threshold for Clear R/W Channel Indicator 清晰信道指示的RSSI阈值 R/W D7 rssi[7] D6 rssi[6] D5 rssi[5] D4 rssi[4] D3 rssi[3] D2 rssi[2] D1 rssi[1] D0 rssi[0] POR Def. — 00h rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] For CCA, threshold is programmed into rssith[7:0] in \"Register 27h. RSSI Threshold for Clear Channel Indicator.\" 对于CCA, 阈值是在\"寄存器27h. 清晰信道指示的RSSI 阈值\"中进行编程的。 After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this channel is above or below the threshold. If the signal strength is above the programmed threshold then the RSSI status bit, irssi, in \"Register 04h. Interrupt/Status 2\" will be set to 1. The RSSI status can also be routed to a GPIO line by configuring the GPIO configuration register to GPIOx[3:0] = 1110. 在报头中评估RSSI后，如果在此信道上的信号强度高于或低于此阈值，则必须作出一个决定。如果信号强度高于编程的阈值，则\"寄存器04h. 中断/状态 2\"中的RSSI状态位irssi将被设置为1，也可以通过配置GPIO配置寄存器为GPIOx[3:0] = 1110，把RSSI状态输送至GPIO线上。 图31 RSSI值与输入功率的关系 9. Reference Design 参考设计 Reference designs are available at www.silabs.com for many common applications which include recommended schematics, BOM, and layout. TX matching component values for the different frequency bands can be found in the application notes ―AN435: Si4032/4432 PA Matching‖ and ―AN436: Si4030/4031/4430/4431 PA Matching.‖ RX matching component values for different frequency bands can be found in ―AN427: EZRadioPRO Si433x and Si443x RX LNA Matching.‖ 关于许多常见应用的参考设计(包括推荐的原理图、清单和布线)可以在www.silabs.com中获取，不同频段的TX匹配元件值可以在应用说明―AN435: Si4032/4432 PA匹配‖ 和 ―AN436: Si4030/4031/4430/4431 PA 匹配‖中找到，不同频段的RX匹配元件值可以在―AN427: EZRadioPRO Si433x和Si443x RX LNA 匹配‖中找到。 10. Application Notes and Reference Designs 应用说明和参考设计 A comprehensive set of application notes and reference designs are available to assist with the development of a radio system. A partial list of applications notes is given below. For the complete list of application notes, latest reference designs and demos visit the Silicon Labs website. 可以获得完整的一套应用说明和参考设计以帮助无线系统的开发，下面给出应用说明的部分列表。关于应用说明的完整列表、最新的参考设计和演示，请访问硅实验室公司网站。 AN361: Wireless MBUS Implementation using EZRadioPRO Devices AN379: Antenna Diversity with EZRadioPRO AN414: EZRadioPRO Layout Design Guide AN415: EZRadioPRO Programming Guide AN417: Si4x3x Family Crystal Oscillators AN419: ARIB STD-T67 Narrow-Band 426/429 MHz Measured on the Si4431-A0 AN427: EZRadioPRO Si433x and Si443x RX LNA Matching AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the EZRadioPRO RF Devices AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequence 图32 TX/RX参考设计图 AN435: Si4032/4432 PA Matching AN436: Si4030/4031/4430/4431 PA Matching AN437: 915 MHz Measurement Results and FCC Compliance AN439: EZRadioPRO Quick Start Guide AN440: Si4430/31/32 Register Descriptions AN445: Si4431 RF Performance and ETSI Compliance Test Results AN448: General Purpose ADC Configuration AN453: Using the EZRadioPRO Calculator and Advanced RX BW Calculations and Settings AN459: 950 MHz Measurement Results and ARIB Compliance AN460: 470 MHz Measurement Results for China AN461:+24 dBm External PA Application Note and Reference Design AN462: Extended battery life using the EZRadioPRO and a DC-DC Buck Converter AN463: Support for Non-Standard Packet Structures and RAW Mode AN466: Si4030/31/32 Register Descriptions AN467: Si4330 Register Descriptions AN361: 采用EZRadioPRO器件的无线MBUS实现方案 AN379: 分集式天线与EZRadioPRO AN414: EZRadioPRO布线设计指南 AN415: EZRadioPRO编程指南 AN417: Si4x3x系列晶体振荡器 AN419: 在Si4431-A0上测得的ARIB STD-T67窄带426/429 MHz AN427: EZRadioPRO Si433x和Si443x RX LNA匹配 AN429: 在F9xx系列MCU上采用DC-DC转换器用于EZRadioPRO RF器件的单电池操作 AN432: 在带回路PN序列的EZRadioPRO上的RX BER(接收位误码率)测量 AN435: Si4032/4432 PA匹配 AN436: Si4030/4031/4430/4431 PA匹配 AN437: 915 MHz测量结果和FCC一致性 AN439: EZRadioPRO快速启动指南 AN440: Si4430/31/32寄存器说明 AN445: Si4431 RF性能和ETSI一致性测试结果 AN448: 通用ADC配置 AN453: 采用EZRadioPRO计算器和先进的RX BW计算和设置 AN459: 950 MHz测量结果和ARIB一致性 AN460: 针对中国的470 MHz测量结果 AN461:+24 dBm外部PA应用说明和参考设计 AN462: 采用EZRadioPRO和DC-DC补偿转换器的扩展电池寿命 Converter AN463: 对非标准数据包结构和RAW方式的支持 AN466: Si4030/31/32寄存器说明 AN467: Si4330寄存器说明 11. Customer Support 客户支持 Technical support for the complete family of Silicon Labs wireless products is available by accessing the wireless section of the Silicon Labs' website at www.silabs.com/wireless. For answers to common questions please visit the wireless knowledge base at www.silabs.com/support/knowledgebase. 对于硅实验室公司无线产品的完整系列的技术支持可以通过www.silabs.com/wireless访问硅实验室公司网站的无线部分获取，关于常见问题的答案，请在 www.silabs.com/support/knowledgebase网址中访问无线电知识库。 12. Register Table and Descriptions 寄存器表和说明 Table 18. Register Descriptions 表格18 寄存器说明 Table 18. Register Descriptions (Continued) 表格18 寄存器说明(续) Note: Detailed register descriptions are available in ―AN440: EZRadioPRO Detailed Register Descriptions.‖ 说明: 详细的寄存器说明可以在―AN440: EZRadioPRO详细的寄存器说明‖中获取。 13. Pin Descriptions: Si4430/31/32 引脚说明: Si4430/31/32 14. Ordering Information 订货须知 Part Number* 零件号 Si4430-B1-FM Description 描述 ISM EZRadioPRO Transceiver ISM EZRadioPRO收发器 ISM EZRadioPRO Transceiver ISM EZRadioPRO收发器 ISM EZRadioPRO Transceiver ISM EZRadioPRO收发器 Package Type 封装类型 QFN-20 Pb-free QFN-20无铅 QFN-20 Pb-free QFN-20无铅 QFN-20 Pb-free QFN-20无铅 Operating Temperature –40 to 85 °C Si4431-B1-FM –40 to 85 °C Si4432-B1-FM –40 to 85 °C *Note: Add an ―(R)‖ at the end of the device part number to denote tape and reel option; 2500 quantity per reel. *注释: 在器件零件号末尾加一个―(R)‖表示卷带选项, 每卷2500个. 15. Package Markings (Top Marks) 封装标识(顶部标记) 15.1. Si4430/31/32 Top Mark Si4430/31/32顶部标记 15.2. Top Mark Explanation 顶部标记说明 Mark Method: 标记方法 Line 1 Marking: 第1行标记 YAG Laser YAG激光 X = Part Number X = 零件号 0 = Si4430 1 = Si4431 2 = Si4432 Line 2 Marking: 第2行标记 R = Die Revision R = 基片修订号 TTTTT = Internal Code TTTTT = 内部代码 YY= Year WW = Workweek YY= 年份 WW = 工作周 B = Revision B1 B = 修订号B1 Internal tracking code. 内部跟踪代码 Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. 由装配处分配, 与开模日期的年份和工作周的最后有效位对应. Line 3 Marking: 第3行标记 16. Package Outline: Si4430/31/32 封装外形: Si4430/31/32 Figure 33 illustrates the package details for the Si4430/31/32. Table 19 lists the values for the dimensions shown in the illustration. 图33表明了Si4430/31/32的封装详情, 表格19列具了在图中所示的尺寸值。 图33. 20脚四列扁平无铅封装(QFN) 因篇幅问题不能全部显示，请点此查看更多更全内容