module counter60(clk_in,clkout,rst,out);
input clk_in,rst;
output [6:0] out;
output clkout;
reg [6:0] out1;
reg [6:0] out2;
reg [3:0] cnth;
reg [3:0] cntl;
reg [7:0] cnt;
always @(posedge clk_in)
begin
if(!rst)
cnt<=8'd0;
else
cnt<=cnt+8'd1;
end
assign clkout=cnt[4];
always @(posedge clkout or negedge rst)
begin
if(!rst) {cnth,cntl}<=8'd0;
else if(cnth==5&&cntl==9) {cnth,cntl}<=8'd0;
else if(cntl==4'd9)
begin
cntl<=4'd0;
cnth<=cnth+4'd1;
end
else cntl<=cntl+4'd1;
end
always @(cnth)
begin
case(cnth)
4'd0:out1=7'b011_1111;//0
4'd1:out1=7'b000_0110;//1
4'd2:out1=7'b101_1011;//2
4'd3:out1=7'b100_1111;//3
4'd4:out1=7'b110_0110;//4
4'd5:out1=7'b110_1101;//5
default:out1=7'b011_1111;//0
endcase
end
always @(cntl)
begin
case(cntl)
4'd0:out2=7'b011_1111;//0
4'd1:out2=7'b000_0110;//1
4'd2:out2=7'b101_1011;//2
4'd3:out2=7'b100_1111;//3
4'd4:out2=7'b110_0110;//4
4'd5:out2=7'b110_1101;//5
4'd6:out2=7'b111_1101;//6
4'd7:out2=7'b000_0111;//7
4'd8:out2=7'b111_1111;//8
4'd9:out2=7'b110_1111;//9
default:out2=7'b011_1111;//0
endcase
end
assign out=(clk_in==1)? out2:out1;
endmodule
`timescale 1ns/1ns
module test();
reg clk_in,rst;
wire out;
initial
begin
clk_in=0;
rst=1;
#5 rst=0;
#30 rst=1;
end
always #5 clk_in=~clk_in;
counter60 m0(.clk_in(clk_in),.rst(rst),.out(out));
endmodule
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