STV0297 datasheet_7346000A

QAM demodulator IC with A/D converter

DATASHEET

Features

IDecodes DVB-C/ITU J83-A and ITU J83-C bitstreams.IHigh-performance integrated A/D converter suitable for direct IF architecture in all QAM (quadrature amplitude modulation) modes.ISupports 16, 32, 64, 128 and 256 point constellations.ISmall footprint package (10 x 10mm2).IVery low power consumption (400 mW typ. at 6.9 Msymb/s).

Confidential IFully digital demodulation.IVariable symbol rates from 0.87 Mbaud to 11.7 Mbaud.

IFront derotator for better low symbol rate performance and relaxing tuner constraints.IIntegrated matched filtering.IRobust integrated adaptive equalizer.IOn-chip FEC with individually by-passable blocks.ITwo AGC outputs suitable for delayed AGC applications (sigma-delta outputs).IIntegrated signal quality monitors, plus lock indicator and interrupt pins.ISystem clock can be generated on-chip from quartz crystal.IEasy control and monitoring via two-wire fast i²C bus.IAdditional private I²C bus (I²C repeater)

dedicated to tuner control for minimum tuner disturbance. Clean three-wire bus repeater also available.IProgrammable clock derived from system clock and available for external use.IParallel and serial output interfaces, with DVB common interface support.ICMOS technology, 3.3 V operation.

TQFP64 (10 x 10 x 1.40 mm)(Full plastic quad flat pack)Order code: STV0297 Applications

ICable set-top boxes.ICable modems.ICable tuners.

July 20027346000A STMicroelectronics Confidential

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

STV0297

Table of contents

Chapter 1Chapter 2

2.12.2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin connections ....................................................................................................................6Pin list ...................................................................................................................................6

Chapter 3

3.13.2

3.2.13.2.23.2.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

A/D converter ........................................................................................................................9Analog AGC control: delayed AGC ......................................................................................9

Dual control point AGC ........................................................................................................................................9Single control point AGC ....................................................................................................................................10AGC pin configuration ........................................................................................................................................10

Confidential 3.33.43.53.63.7

IF to baseband ....................................................................................................................10Nyquist filtering and symbol timing recovery ......................................................................11Digital AGC .........................................................................................................................12Carrier recovery loop and adaptive equalizer .....................................................................12Differential decoding and symbol-to-byte mapping ............................................................12Convolutional de-interleaver ...............................................................................................12Reed-Solomon decoder ......................................................................................................13Sync byte inversion and descrambling ...............................................................................13Transport stream output interface ......................................................................................13

DVB common interface ......................................................................................................................................13Alternative parallel format ..................................................................................................................................14Serial format .......................................................................................................................................................15

3.83.93.103.11

3.11.13.11.23.11.3

3.12

3.12.13.12.2

Signal quality monitors .......................................................................................................16

Integrated BER tester .........................................................................................................................................16C/N estimator .....................................................................................................................................................16

3.133.14

3.14.13.14.2

I²C control bus ....................................................................................................................17I²C and 3-wire bus repeater ................................................................................................17

I²C repeater ........................................................................................................................................................17Three-wire bus repeater .....................................................................................................................................17

3.15

3.15.13.15.23.15.33.15.4

Hardware lock indicator, interruptgenerator, auxiliaryPWMgenerator .............................19

Pin multiplexing ..................................................................................................................................................19Interrupt requests ...............................................................................................................................................19Hardware lock indicators ....................................................................................................................................19Auxiliary PWM generator ...................................................................................................................................19

3.16Auxiliary clock output ..........................................................................................................20

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STV0297Chapter 4Chapter 5Chapter 6Chapter 7

Register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

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DescriptionSTV0297

1Description

The STV0297 is a complete single chip QAM (quadrature amplitude modulation) demodulation solution that performs sampled IF to MPEG-2 block processing of QAM signals, intended for the digital transmission of compressed television, sound, and data services over cable. It is fully compliant with the DVB-C specification (ETS 300 429, “Digital broadcasting systems for

television, sound and data services — Framing structure, channel coding and modulation — Cable Systems”) or ITU J83-A and can also decode ITU J83-C (Japanese scheme) bit streams. It can handle square (16, 64, 256-QAM) and non-square (32, 128-QAM) constellations.The chip integrates an A/D converter that delivers the required performance to handle up to 256-QAM signals in a direct IF sampling architecture, thus eliminating the need for external

downconversion. The IF can be up to 45MHz while the STV0297 allows the sampling clock to be freely selected off a given range (and meeting constraints derived from SAW filter and symbol rate characteristics). All further processing is fully digital, which means that no external feedback loop is required. The STV0297 is capable of coping with a wide range of symbol rates, ranging from the highest practical rates to rates as low as 0.87Msymb/s, even in the presence of a significant frequency offset.

Confidential It is, therefore, an excellent candidate for integration in set-top-boxes, cable modems and cable tuners.

In addition to all of the necessary demodulation and FEC functions required for recovery of the QAM modulated bit streams with outstanding BER results, it also includes several features that give simple and immediate access to various quality monitoring parameters or lock status. The STV0297 also provides outputs, such as delayed AGC or noise-free I²C bus dedicated to tuner control, that will ease the design of good quality application boards.The STV0297 outputs error-corrected MPEG-2 transport streams and complies with the DVB Common Interface format, with programmable data clock frequency. It also interfaces seamlessly to the packet demultiplexers embedded in the ST ST20-TPx or STi55xx, and to the STV0191 cable return channel IC. 4/41STMicroelectronics Confidential 7346000A

STV0297

Figure 1: STV0297 block diagram

Description

STV0297Initial demodulatorSymbol timing recoveryand Nyquist filteringA/D converterDigital AGCCarrier recoveryand adaptive equalizerANAIN42ANAIND41Signal qualityestimatorAGC132AGC12B35AGC233Lock status andinterrupt request generatorGeneral-purposePWM generatorTo all blocksClockgeneratorTestcontrollerAGC andDelayed AGCBER testerIT_LOCK6IT_PWM64De-interleaver,Reed/Solomon FEC decoder,DescramblerTo all internalregistersRAMRESET7Confidential AUXCLK2I²C interfaceand I²C repeaterOutputformatter 49502728293010141525M_DATA[7:0](pins 23 to 16)M_VALM_SYNCM_CKOUTM_ERRSCLTSDATSCLXTAL2TEST[9:0]SDACKEXT 7346000ASTMicroelectronics Confidential5/41

Pin informationSTV0297

2

2.1

Pin information

Pin connections

Figure 2: STV0297 pinout

IT-PWMCKEXT494847464544434241 403938373635343317181920212223242526272829303132646362616059585756555453525150VSSIAUXCLKVSSETEST9VDDEIT_LOCKRESETXTAL2TEST7TEST6TEST5TEST4TEST3TEST2TEST1TEST0VDDEVSSEVDDIVDDIVSSI12345678 910111213141516VSSETWBEN_INVSSA_SHIELDGNDA2RGNDGNDA1ANAINANAINDVCCAVRHFVRLFVDDAVDDA_SHIELDAGC12BVDDEAGC2Confidential TEST8VSSIM_ERRVDDIVSSEVDDEM_CKOUT M_VALM_DATA[0]SDATSCLM_SYNCM_DATA[1]M_DATA[2]M_DATA[3]M_DATA[4]M_DATA[5]M_DATA[7]SCLTSDA2.2Pin list

Open-drain programmable outputs can be configured by software to behave either as normal CMOS push-pull outputs, or as open-drain outputs.

Tri-state capable outputs can be disabled (high impedance) by software.

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M_DATA[6] 7346000A

AGC1VDDIVSSEVSSISTV0297

Table 1: STV0297 pin listPin

Name

Type

Description

Pin information

DriveNotes

Reset and clock749502

NRESETCKEXTXTAL2AUXCLK

IIOO

Hardware reset, active low.

Crystal oscillator input (from crystal) or external clock input.

Crystal oscillator output (to crystal).Auxiliary clock derived from CKEXT by division (integer ratio). Can be disabled.

---3 mA

5VT

A/D converter3938404537

VRHFVRLFVCCAGNDA2VDDAGNDA1VDDA_SHIELDVSSA_SHIELDANAINANAINDRGNDAnalog referenceAnalog referencePower supplyGroundPower supplyGroundPower supplyGroundAnalog inputAnalog input Power supplyTop A/D voltage reference.Bottom A/D voltage reference.Connects externally to positive analog supply (3.3 V typ.).

Connects externally to analog ground.Connects externally to positive analog supply.

Connects externally to analog ground.For A/D cell shielding.Connect to positive analog supply.For A/D cell shielding. Connect to analog ground.Analog IF signal, 1 VPP typ.Pseudo-differential Input.

Connects externally to analog ground.

Confidential 4336464241

44

I2C interface28273029

SCLSDASCLTSDAT

I

I/O, open-drainOpen-drain programmableI/O, open-drain

Private I²C bus (clock and serial data) for minimum noise exchanges with sensitive components (especially the tuner). Can also be used as 3-wire bus clock to tuner (forced open-drain in this case) and data to tuner.I²C bus (clock and serial data).

-4 mA-4 mA

5VT5VT

AGC interface32

AGC1

O, open-drain programmableO, open-drain programmable

First sigma-delta output for AGC in dual AGC application (typically tuner gain control) = delayed AGC.

Second sigma-delta output for AGC in dual AGC application (typically IF gain stage control) = immediate AGC. Also pin to use in single AGC applications.Complement of either ACG1 or AGC2 (to obtain a differential AGC), output in that case. Can also be configured as 3-wire bus data from master.3-wire bus enable from master

3 mA

5VT

33AGC2 3 mA 5VT

35AGC12B

I/O, open-drain programmable

4 mA 5VT

47TWB_ENINI 5VT

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Pin information

Table 1: STV0297 pin listPin

Name

Type

Description

Drive

STV0297

Notes

MPEG/TS output interface14

M_CKOUT

O, Tri-state capable

Output byte clock / Output serial bit clock. Programmable frequency if

configured for DVB Common Interface format.

Transport stream MPEG data to

transport IC/packet demultiplexer either in parallel format or in serial format (on M_DATA[0] in this case, maximum serial rate = 2.fCKEXT). Sync word can optionally be stripped off.MPEG-TS output data valid flag.MPEG/TS frame start pulse. Indicates the start of a Reed-Solomon decoded packet.

Reed-Solomon error (uncorrected error in current packet if high).

4

23 to 16M_DATA[7:0]O, Tri-state capable3(4)

1525

M_VALM_SYNC

O, Tri-state capableO, Tri-state capable

44

10M_ERRO, Tri-state capable4

Confidential Interrupt and status pins64

IT_PWM

O, Open-drain programmable

PWM = Programmable general purpose pulse width modulator.IT=Interrupt. Maskable interrupt triggered by a lock or an unlock event in the de-interleaver sync detector or in the descrambler sync detector or by the channel scanning function.

Can also be configured as 3-wire bus Enable to tuner (forced open-drain in that case). Selection between these three uses by user register.

LOCK = Lock indicator. Can be

programmed to reflect lock status of descrambler sync detector (ultimate synchronization block in the data flow) or of intermediate stages.

IT=Interrupt. Same IT signal as described above. Can also be

configured as 3-wire bus Clock from master. Selection between these three uses by user register.

4

5VT

6IT_LOCKI/O, Open-drain programmable

45VT

Test interface4, 8, 63, 61, 60, 58, 56, 55, 52, 51

TEST[9:0]

I

Reserved for test.

Tie to GND for normal use.

Core and I/Os power supply11, 24, 53, 621, 9, 31, 545, 13, 34, 573, 12, 26, 48, 59

VDDIVSSIVDDEVSSE

Digital power supply (positive)

Digital power supply (ground)

Digital power supply (positive)

Digital power supply (ground)

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STV0297Functional description

3

3.1

Functional description

A/D converter

The analog/digital converter (ADC) is a high-performance ADC capable of sampling the

intermediate frequency produced by CATV tuners at sampling rates up to 36MHz. A large range of tuner intermediate frequencies can be processed, including 36MHz, 44MHz and 7.2MHz. ADC inputs are pseudo-differential, the nominal input voltage is 1 VPP, and the input signal must be centered on 1 V DC.

In case of ADC overflow, the mean overflow rate is available from user registers 0x37 and 0x38.

3.23.2.1Analog AGC control: delayed AGCDual control point AGCThe STV0297 has two PWM outputs for AGC, typically one for tuner gain control (AGC1) and the other for IF stage gain control (AGC2). The analog gain control commands are obtained by simple low-pass filtering of these PWM signals. Additionally, a third pin (AGC12B) is available to provide a differential AGC output (with respect to AGC1 or AGC2, programmable), refer to Figure3.Confidential Figure 3: Differential AGC output Providing two AGC control points allows the tuner to be operated as much as possible at maximum gain to obtain best performance (Figure4). For lower RF level signals, the AGC1 PWM rate is fixed at its maximum allowed value. For higher RF level signals, AGC1 and AGC2 are both active, AGC2 is predominant. The take-over point is programmable and defined by a threshold set on AGC2. The loop response is user-programmable and controls the overall AGC action; the input reference level is also programmable (registers 0x30 to 0x4B).

AGC1 and AGC2 PWM rates can be saturated to minimum and maximum values. They can be frozen independently under software control, or automatically on detection of AGC lock by the STV0297. When both AGCs are active, the overall action is distributed over AGC1 and AGC2 with a ratio that is user-defined.

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Functional description3.2.2

Single control point AGC

STV0297

A single AGC control point may still be used if desired. The pin to use in this case is AGC2 (plus optionally AGC12B).

Figure 4: AGC control level

AGC control level (PWM rate)AGC2 (max.)AGC1 (max.)AGC2 thresholdAGC2 (min.)AGC1 (min.)*Set by µCTake-overpointAGC2AGC1RF input level3.2.3AGC pin configurationThe AGC outputs can be programmed to behave either as normal CMOS outputs or as 5 V tolerant open-drain outputs. The latter option enables the use of 5 V AGC range tuners without any additional amplification by tying a pull-up resistor to 5 V.Confidential 3.3IF to basebandThe signal centered on tuner IF is down-converted by A/D subsampling (A/D is clocked at frequency fCKEXT). The replica used is typically centered on the sampled IF, f1:

f1=fTUNER-fCKEXTFor example:fTUNER=36MHz,fCKEXT= 28.8MHz => f1=7.2MHz.

If preferable, it is also possible to use another replica such as f1=fTUNER-2fCKEXT, or to

process low IF (for example,7.2MHz) that do not need further downconverting. The sampling clock can be freely chosen as long as it introduces no aliasing, so depends on the SAW filter characteristics and symbol rate. Refer to Figure5.

This leads to two conditions to take into account, the potential aliasing from the adjacent replicas at higher and at lower frequency.G-f1+ WSTOP/2< f1-FS/2.(1+ α)

for instance, when working with f1= FTUNER- FCKEXT:FCKEXTand,

GFCKEXT-f1-WSTOP/2>f1+FS/2.(1+α)

for instance, when working with f1=FTUNER-FCKEXT:FCKEXT>2.FTUNER/3+FS/6.(1+α)+WSTOP /6or, when working with f1=FTUNER-2.FCKEXT:FCKEXT>2/5.FTUNER+FS/10.(1+α)+WSTOP /10

where WSTOP is the SAW filter stop band, and FS is the symbol rate.

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STV0297Functional description

This sampled IF is then downconverted from f1 to quasi-baseband by a programmable

quadrature demodulator. This block is able to downconvert to baseband any signal within range 0 to fCLK/2. It can therefore be used as a virtual tuner to bring to baseband signals whose carrier is not at the center of the channel. This is specially interesting for low symbol rates SCPC situations where this allows to speed up channel switching and removes adjacent channel interference problems.

Figure 5: Frequency spectra after direct downconversion

PSDWSTOPWPASSSAW filter templateUseful signal spectrumfs(1 + α)-f10f1ffCKEXT/2fCKEXT - f1fCKEXT= fTUNER - fCKEXTConfidential It also allows to compensate for locally generated frequency offset (for example, due to tuner) before matched filtering, so that even large offsets are no longer a problem. This may for example enable the use of larger tuner steps (which generally means lower phase noise).It should be noted however, that using the fully programmable quadrature demodulator limits the symbol rate as follows:FCKEXT>3.58 x FS(1 + α)Should this be a problem in some very high symbol rate applications, an alternative, less flexible quadrature demodulator is available (selection through register0x25), for which the above relation needs not hold but which always requires: f1=FCKEXT /4.

The initial derotator can also introduce a frequency mirroring effect to cancel spectral inversion possibly introduced by the network.

Any phase or frequency offset remaining after this stage is coherently tracked by the derotator present further down the chain.

The IF-to-baseband stage is coupled to an automatic channel scanning function. The demodulation frequency starts from a given value and then is automatically and regularly

increased by a programmable step. The latency between steps is user-programmable, and it is possible to generate an interrupt on pins IT_PWM or IT_LOCK upon every frequency jump. The STV0297 can be instructed to automatically stop scanning the channel upon lock detection, alternatively frequency scanning can be fully user controlled (registers0x25 to 0x2F).

3.4Nyquist filtering and symbol timing recovery

The quasi-baseband complex data stream is filtered by a complex square-root Nyquist filter, which can cope with 0.13 to 0.15 transmit roll-off factors.

The correct symbol values at optimum sampling instant are obtained by time-domain interpolation under the control of a timing loop. This loop is a second-order loop whose parameters are controlled by user registers 0x50 to 0x5F.

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Functional descriptionSTV0297

3.5Digital AGC

The digital AGC stage adjusts the amplitude of the demodulated symbols to compensate for the energy that has been filtered out by the Nyquist interpolating filter (including any co-channel interference), and for the gain of this same filter which depends on the ratio between the (fixed) sampling clock frequency and the (arbitrary) symbol rate. Control is via registers 0x70 to 0x7F.

3.6Carrier recovery loop and adaptive equalizer

The carrier recovery loop (CRL) cancels the residual carrier frequency and phase offset after initial demodulation. It is a second-order closed loop. Additionally it includes a sweep function to be able to search a relatively wide band for exact derotation frequency.

When using the sweep feature, start frequency, sweep rate and directions are all programmable. Practical uses can range from simple linear sweep to more sophisticated algorithms such as zigzag search (under software control).

Chip performance may be optimized by optimizing the respective uses of CRL and initial

derotator (for example, if the CRL locks for a given offset value, it is possible to transfer this offset cancellation from CRL to initial derotator before Nyquist filtering, the latter being then better matched to the signal actually received).

Confidential The channel equalizer is able to adaptively cancel a wide variety of echoes and linear channel distortions. It starts up with a blind equalization algorithm, and once locked switches to a decision-directed LMS algorithm.

The carrier recovery loop parameters are controlled via registers 0x60 to 0x6F, the equalizer is set up with registers 0x00 to 0x0F.

3.7Differential decoding and symbol-to-byte mappingThe STV0297 differentially decodes the symbol stream as required by DVB-C/ITUJ83-A and ITUJ83-C specifications. The symbol stream (4-bit symbols for 16-QAM up to 8-bit symbols for 256-QAM) is turned into a byte stream following these same specifications, since the subsequent FEC (forward error correction) operates on bytes.

3.8Convolutional de-interleaver

To reduce any burst or impulse noise and increase the correction power of the Reed-Solomon FEC code, the bytes are interleaved after R/S encoding at the transmitter side, so must be

de-interleaved before R/S decoding at the receiver side. An interleaved frame being delimited by MPEG-2 sync bytes and inverted sync bytes (preserving the periodicity of 204 bytes), the

convolutional de-interleaver is able to synchronize by locking onto these words. Default behavior of the state machine that declares acquisition/tracking based on the data received can be modified if desired (registers 0x90 to 0x9F).

Integrated in the STV0297 is a Forney type de-interleaver, default interleaving depth is 12 and cell depth is 17 (which are the values specified for DVB-C/ITU-J83-A and C). However smaller depths can also be programmed to fit reduced latency applications. It is also possible to bypass the de-interleaver (registers 0xB0 to 0xBF).

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STV0297Functional description

3.9Reed-Solomon decoder

The Reed-Solomon decoder performs [t=8,(n,k)=(204,188)] decoding as described in DVB / ITU-J83-A and C standards.

Note that the R/S block can be required not to perform any correction to allow external evaluation of raw bit error rates (BER before R/S correction), see register 0xDF.

3.10Sync byte inversion and descrambling

The descrambler works according to the DVB-C/ITU J83-A and ITU J83-C specifications and is based on polynomial 1+x14+x15. It is synchronized by the inverted sync bytes present at the start of every eighth transport packet. In the derandomized data stream supplied to the output interface, the inverted sync byte is reinverted back to normal.Control of the descrambler is through registers 0xC0 to 0xDF.

3.11Transport stream output interface

The STV0297 offers the possibility to output data according to the DVB-specified common

interface format, or in a specific parallel format (where there are no invalid bytes inserted within a burst of 188 valid data bytes of a same packet), or in serial form at instantaneous bit rates up to 60MHz.

Confidential The pins forming the MPEG/TS output interface are M_CKOUT, M_DATA[7:0], M_VAL, M_SYNC and M_ERR.

Their role is as follows:

GM_CKOUT: data clock with programmable polarity. According to the format selected, it can be either continuous or punctured. Refer to Sections 3.11.1 to 3.11.3.

GM_VAL: strobe signal that indicates whether the byte (bit in serial mode) supplied on M_DATA[7:0] (M_DATA[0] in serial mode), to be clocked in by the active edge of M_CKOUT, is one of the 188 valid bytes of the MPEG packet.GM_SYNC: this signal flags the first valid byte (bit in serial mode) of an MPEG/TS packet.GM_ERR: this signal goes high during transmission of an MPEG/TS packet if this packet contains errors that could not be corrected by the R/S decoder.The output interface formatter is controlled via registers 0xC0 to 0xCF.

3.11.1DVB common interface

The clock supplied on M_CKOUT is continuous and has programmable frequency and polarity (Figure6). Frequency is specified by giving the high level and low level pulse durations in terms of cycles of a base clock at either the system clock frequency (fCKEXT) or twice this frequency (2·fCKEXT). The STV0297 requires the common interface clock frequency to always be (strictly) greater than the symbol rate:

fM_CKOUT>fSin all QAM modes.By choosing appropriate division ratios, a number of output clock frequencies between 5 and 9MHz with duty cycle between 40 and 60% are available.

When common interface format is selected, the M_ERR flag is still supplied although it is not actually required by the DVB-CI specification.

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Functional description

3.11.2Alternative parallel format

STV0297

The other parallel format offered by the STV0297 is such that the STV0297 clocks out exactly 188 or 204 bytes (user programmable) per MPEG/TS packet. Any data byte clocked out is either a valid MPEG/TS data byte or (optionally) a RS redundancy byte, in any case the 188 valid data bytes of a given packet are clocked out in a row (Figure7A and Figure7B).

M_CKOUT in this mode is not continuous. It is a punctured data clock at byte frequency on average. This clock may be running during the 188 data bytes and the 16 parity bytes, or during the 188 valid data bytes only and be inactive during the 16 parity bytes (user programmable).

Figure 6: DVB common interface format

M_CKOUTM_VALM_SYNCM_DATA47Confidential Figure 7A: MPEG output waveforms in parallel mode according to configuration bitsNO ERRORM_CKOUTwith bit 'ct_nbst' = 1 and bit 'ckout_par' = 1UNCORRECTED PACKETNO ERROR with bit 'ct_nbst' = 0 and bit 'ckout_par' = 1with bit 'ct_nbst = 1 and bit 'ckout_par' = 0 with bit 'ct_nbst' = 0 and bit 'ckout_par' = 0204 clock pulsesM_VAL188 MPEG bytesM_DATA[7:0]with bit 'ct_nbst' = 116 parity byteswith bit 'ct_nbst' = 0M_SYNCM_ERRwith bit 'ct_nbst' = 1with bit 'ct_nbst' = 014/41STMicroelectronics Confidential 7346000A

STV0297Functional description

Figure 7B: MPEG/TS output interface waveforms and timings in parallel mode (with bit CKOUT_PAR = 0 in register 0xC0)

tCLKCKEXTM_CKOUTtP_MtCLKtCLKN x tCLKM_DATA[7:0]3 tCLK or moreM_VALM_SYNCM_ERRFirst byte of an MPEG/TS packet3 tCLK or more3.11.3Serial formatIn this mode the data is supplied as a serial bit stream on M_DATA[0] and the clock on M_CKOUT is a bit clock (Figure8A and Figure8B). The serial clock is a clock derived either from the master clock or from a double-frequency clock (Figure13). Confidential This determines the maximum achievable throughput. For example, if the master clock (supplied on CKEXT) is 28.8MHz, in the first case the maximum throughput is 28.8Mbit/s, in the second case it is 57.6 Mbit/s.Figure 8A: MPEG output waveforms in serial mode according to configuration bitsNO ERRORUNCORRECTED PACKETNO ERROR M_CKOUTwith bit 'ct_nbst' = 1 and bit 'ckout_par' = 1with bit 'ct_nbst' = 0 and bit 'ckout_par' = 1with bit 'ct_nbst' = 1 and bit 'ckout_par' = 0with bit 'ct_nbst' = 0 and bit 'ckout_par' = 0204 x 8 = 1632 clock pulsesM_VAL188 x 8 = 1054 MPEG bits16 x 8 = 128 parity bitsM_DATA[0]with bit 'ct_nbst' = 1with bit 'ct_nbst' = 0M_SYNCDuration = 1 bitM_ERRwith bit 'ct_nbst' = 1with bit 'ct_nbst' = 0 7346000ASTMicroelectronics Confidential15/41

Functional descriptionSTV0297

Figure 8B: MPEG/TS output interface waveforms and timings in serial mode (with clock doubler On and bit CKOUT_PAR=1 register 0xC0)

CKEXTM_CKOUTtCLK/2tCLKtPULSEb6b5b1b0b7b6M_DATA[0]M_SYNCM_VALM_ERRb7Possible gapFirst serialized byte of an MPEG/TS packet (8 consecutive bits)2nd serialized byte...3.12Signal quality monitors

3.12.1Integrated BER tester

Confidential The STV0297 offers easy access to byte error and bit error information. This information relates to errors before R/S correction.

Two operating modes are available, selected by user-register (see registers 0xA0 to 0xAF):Gthe first mode is for bit error or byte error rate (raw BER) measurements. The user programs the duration over which the errors are to be counted (expressed as a number of data bytes, NB, including R/S parity bytes) and selects whether bit errors or byte errors are to be stored in register ERRCNT.

Bit BERT_ON is then set to launch the BER measurements. This bit is automatically cleared when the specified number of data bytes have elapsed. It is then easy to compute the BER:-Byte error rate = ERRCNT/NB,-Bit error rate = ERRCNT / (8 x NB).Gthe second mode counts bit or byte errors with no automatic stop.

When BERT_ON is set, the error counter is cleared and starts accumulating the errors.

BERT_ON must be explicitly reset by the user to stop accumulation. In case of saturation of the counter before BERT_ON is cleared, the counter stays stuck at its maximum value (no roll-over).

3.12.2C/N estimator

A dedicated register provides a measure of the mean distance between calculated constellation points and mapped values. In other words it measures the spread of constellation points around their ideal values.

A look-up table allows to easily correlate the measured value to an equivalent noise degradation for each QAM mode and gives valuable information on the signal quality.

16/41STMicroelectronics Confidential 7346000A

STV0297Functional description

3.13I²C control bus

The STV0297 is controlled via an I²C bus and is a pure slave. Its 7-bit chip address is 0011100, so its 8-bit write address is 0x38 and its 8-bit read address is 0x39.

The I²C interface supports fast I²C protocol up to 400kHz and potentially much faster(fCKEXT/16 max.). Write and read operations are described in Figure9A and Figure9B.

Figure 9A: I²C write operation

SCLSDAStartI2C Slave AddressR/WACK bySTV0297SCLSDAD7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0Base AddressACK bySTV0297Data Byte 1ACK bySTV0297Data Byte 2ACK bySTV0297Data Byte 3ACK bySTV0297Data Byte nACK bySTV0297StopFigure 9B: I²C read operationSCLConfidential SDAStartI2C Slave AddressR/WACK byA7A6A5A4A3A2A1A0Base AddressACK bySTV0297StopSTV0297SCLSDAStartI2C Slave AddressR/WACK bySTV0297D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0 Data Byte 1ACK bymicroData Byte nACK bymicroStop3.14

3.14.1I²C repeater

This block is intended to remove all unnecessary I²C messages to the tuner and thus improve tuner performance. The tuner connects to pins SCLT and SDAT (Figure10). When enabled, the repeater behaves as a fully bidirectional link between the main I²C bus (SCL, SDA) and the private bus (SCLT, SDAT). When disabled, pins SDAT and SCLT are completely isolated from the main I²C bus and are inactive (high level).

The I²C repeater is enabled for one single access following setting of an enable bit in the user registers. Every time a message needs to be exchanged with the tuner, this bit should be set first and then it is valid until detection of the stop condition of the next message (so page mode access to the tuner is possible). The message to the tuner is sent exactly as if the tuner was directly connecting to the micro’s I²C bus.

SDAT is open-drain and SCLT can be programmed to behave either as open-drain or normal push-pull CMOS buffer. The reset and idle states of these pins are high level (open-drain pulled up by external resistor).

Use of the I²C repeater puts some restrictions on the range of clock frequencies that can be output on pin AUXCLK (refer to Section3.16 and the description of register 0x87).

I²C and 3-wire bus repeater3.14.2Three-wire bus repeater

The frequency synthesizers of some tuners are controlled via a three-wire bus. The STV0297 may be used as a three-wire bus repeater. In this case, the pins connecting to the tuner are made

7346000ASTMicroelectronics Confidential17/41

Functional descriptionSTV0297

open-drain like, so they can be pulled up to a clean power supply to avoid pollution of the frequency synthesizer.

The three-wire bus repeater is unidirectional (from master to tuner) and gates out any signal present on the three-wire bus clock or data while three-wire enable pin is low. The repeater is enabled by a control bit in user register 0x86. Figure11A shows pin connections when using the three-wire bus repeater and Figure11B the waveforms. Note that pins IT_LOCK, IT_PWM and AGC12B become unavailable for normal user when using the three-wire bus repeater feature.

Figure 10: I²C repeater

I2CMASTER2827SCLRepeaterON/OFFSCLT3029TUNERSDASTV0297InternalRegistersSDATConfidential Figure 11A: Three-wire bus repeater connections 476 64303527Figure 11B: Three-wire bus repeater waveforms

TWBEN_INTWBCK_IN = IT_PWMTWBDAT_IN = AGC12BTWBEN_OUT = IT_LOCKTWBCK_OUT = SCLTTWBDAT_OUT = SDAT18/41STMicroelectronics Confidential 7346000A

STV0297Functional description

3.15Hardware lock indicator, interruptgenerator, auxiliaryPWMgenerator

3.15.1Pin multiplexing

There are two pins dedicated to these functions: IT_LOCK and IT_PWM. Figure12 describes pin multiplexing. Both pins can be programmed to behave either as normal CMOS buffers or as open-drain outputs (register 0x87).

Note:

LOCK and IT information is also available from status registers.

Figure 12: IT, LOCK and PWM multiplexing

Control Bitsin User RegistersITLOCK_SELLockStatusInterruptRequestProgrammablePWMLockITPWM0101ITLOCK_OD6IT_LOCK64IT_PWMConfidential ITPWM_SELITPWM_OD(controls open-drainbehaviour) 3.15.2Interrupt requests The STV0297 can be instructed to generate interrupt requests to an external microcontroller on pin IT_LOCK or pin IT_PWM upon occurrence of the following events:Gwhen the channel scanning function is on (see Figure3.3 and register0x2x): every time the STV0297 switches from one demodulation frequency to the next,Gon lock or unlock of the descrambler sync detector and/or the de-interleaver sync detector (seeregister0x85). Interrupts are active low and are cleared by microcontroller access.

3.15.3Hardware lock indicators

The STV0297 can also output the following lock information on pin IT_LOCK according to register 0x86:

Gcomplete chip is in lock (descrambler sync detector is in tracking mode),Gequalizer has fully locked (has entered final stage of LMS algorithm),Gequalizer is in blind mode / in LMS mode,Ganalog AGC has locked.

These can also be used as interrupt request by an external microcontroller.

3.15.4Auxiliary PWM generator

A fully programmable 16-bit general purpose PWM generator is included in the STV0297. It is controlled by registers 0x4A and 0x4B.

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Functional descriptionSTV0297

3.16Auxiliary clock output

It is possible to output an auxiliary clock derived by division of input clock CKEXT on pin AUXCLK (see Figure13). The division ratio is integer and programmable from 1 to 8. This clock may be used to replace a crystal oscillator in the target application.

Figure 13: Clocks

CKEXT49XTAL250To CoreTo SerialMPEG/TSOutputInterfaceOSCILLATOR01x 2UXCLK2÷ Mckx2disckx2sel(Reg. 84)(Reg. 84)Reg. 87Confidential 20/41STMicroelectronics Confidential 7346000A

STV0297Register list

4Register list

Note:1All register addresses are hexadecimal values. For register contents, the format is denoted as

follows: 0xNN for hexadecimal, 101 for binary, 0dNN for decimal.

2Suggested values for register programming are intended to serve as indications, in some cases departing from these values may give better performance or behavior.3Signed values are values that should be encoded using 2’s complement format.

4When a programmable parameter requires more than 8 bits and therefore occupies several registers, most significant bytes correspond to greatest addresses (that is, lowest significant byte appears first in this list)

NameAddBitSignaldescriptionEqualizer: constellation quality estimatorEQU_0Reset: 0x090x00[7][6:4]ReservedMODE_SELECT000: 16-QAM001: 32-QAM100: 64-QAM010: 128-QAM011: 256-QAMQAM mode selection. May be overridden by automatic constellation state machine, refer to register0x89. If this state machine is enabled (AUTOCONSTEL_EN = 1 in register0x89) then MODE_SELECT reflects the QAM mode being tried by the state machine.U_THRESHOLDOnce in LMS mode, the equalizer gradually decreases the adaptation step size down to 2(-u_threshold).Confidential [3:0] EQU_1Reset: 0x690x01[7:4][3:0]INITIAL_UInitial adaptation step used when switching to LMS mode is 2(-initial_u).BLIND_UAdaptation step used as long as equalizer is in blind mode is 2(-blind_u).EQU_2EQU_3Reset: 0x000x020x03[7:0][7:4][3:2]ReservedReservedEQ_COEFF_CTL11: Force immediate enabling of equalizer coefficient update process.10: Disable equalizer coefficient update process.0X: no forcing.EQ_FSM_CTL11: Force immediate enabling of state machine controlling blind/LMS equalizer operation.10: Disable state machine controlling blind/LMS equalizer operation, force blind mode.0X: no forcing. ReservedNBLIND:0: blind equalization is in progress,Read-only bitReservedReserved[1:0]EQU_4Reset: 0x000x04[7:1][0]1: it is LMS (steps 1 and 2)EQU_5EQU_60x050x06 7346000ASTMicroelectronics Confidential21/41

Register listSTV0297

NameEQU_7Reset: 0x00Add0x07Bit[7:0]SignaldescriptionNOISE_EST_LOLow byte of the internal noise estimation accumulator. The contents of this accumulator is correlated with the spreading of the decoded constellation: it is a measure of the mean distance between calculated points and mapped values. Using a look-up table, an equivalent noise degradation can be calculated (equivalent C/N estimation).NOISE_EST_HIHigh byte of the internal noise estimation accumulator. See register 0x07.EQU_80x08[7:0]Quadrature demodulatorINITDEM_0Reset: 0x000x20[7:0]DEM_FQCY_LOLow byte of the value that gives the initial demodulation frequency:demodulation frequency = DEM_FQCY_HI + LO x Fclk / 216.(Therefore resolution = Fclk/216, for example, 440 Hz for Fclk = 28.8 MHz).INITDEM_1Reset: 0x00INITDEM_20x22[7:0]0x21[7:0]DEM_FQCY_HIHigh byte of the value that gives the initial demodulation frequency. Refer to register0x20.LATENCYDefines the duration of each step when using the frequency scanning feature. The effective latency expressed with the system clock period Tclk as unit is: 65536 x LATENCY(at Fclk=28.8MHz, min = 2.36ms, max = 600ms).SCAN_STEP_LOLow byte of SCAN_STEP (unsigned 14-bit value) which defines the step between two successive demodulation frequencies tried: (SCAN_STEP / 216) x Fclk.INITDEM_40x24[7]CHSCANITENIf 1, a channel scanning interrupt (CHSCANIT) is generated (to output on pins IT_LOCK or IT_PWM) every time LATENCY (register0x22) elapses.CHSCANITSOFTControls the value of CHSCANIT. Clearing this bit is the only way to clear the CHSCANIT interrupt. This bit overrides CHSCANITEN allowing it to control the interrupt pin whatever the interrupt enabling status.SCAN_STEP_HISix MSBs of SCAN_STEP (unsigned 14-bit value). Refer to register0x23.IN_DEMOD_ENIf 1, quadrature demodulation before Nyquist matched filtering is performed by the programmable initial demodulator. If 0, it is performed using a simpler sequencer which always requires Fclk = 0.8 x Ftuner. In this case, all other bits in registers 0x20 to 0x25 are irrelevant.SCAN_ONIf 1, enables the frequency scanning feature (IN_DEMOD_EN must be 1 too).AUTOSTOPIf 1, frequency scanning (when enabled) automatically stops as soon as the IC has found a signal to lock onto and enters tracking state.SCALE_ATogether with SCALE_B, controls the scaling factor applied in the initial demodulator so that its overall gain is unity. Overall gain is proportional to:2-11 + 2-13.[2(1 + SCALE_A)+2SCALE_B]Suggested value: 0.SCALE_BTogether with SCALE_A, controls a scaling factor applied in the initial demodulator so that its overall gain is unity. See above.Suggested value: 10.ReservedConfidential Reset: 0x00 INITDEM_3Reset: 0x000x23[7:0] Reset: 0x40[6][5.0]INITDEM_5Reset: 0x080x25[7][6][5][4][3:2][1:0]22/41STMicroelectronics Confidential 7346000A

STV0297Register list

NameAddBitSignaldescriptionAnalog AGCs, A/D overflow monitor, General-purpose PWMDELAGC_0Reset: 0x000x30[7:0]AGC2MAXDefines the maximum PWM rate allowed for AGC2 as: max AGC2 PWM rate = AGC2MAX/0xFF x 100% = AGC2MAX/0d255 x 100%.Examples: if AGC2MAX = 0xFF: max rate = 100% (i.e. flat),if 0xBF: max rate = 75%.AGC2MINDefines the minimum PWM rate allowed for AGC2 as: min. AGC2 PWM rate = AGC2MAX/0xFF x 100% = AGC2MIN/0d255 x 100%.Examples: if AGC2MIN = 0x00: min. rate = 0% (i.e. flat),if 0x40 min. rate = 25%.AGC1MAXDefines the maximum PWM rate allowed for AGC1 as: max. AGC1 PWM rate = AGC1MAX/0xFF x 100% = AGC1MAX/0d255 x 100%.Examples: if AGC1MAX = 0xFF: max. rate = 100% (i.e. flat), if 0xBF: max. rate = 75%.AGC1MINDefines the minimum PWM rate allowed for AGC1 as: min. AGC1 PWM rate = AGC1MAX/0xFF x 100% = AGC1MIN/0d255 x 100%.Examples: if AGC1MIN = 0x00: min. rate = 0% (i.e. flat),if 0x40 min. rate = 25%.RATIO_ARATIO_BRATIO_CFor strong RF signals, AGC1 is allowed to decrease from its maximum (nominal) level and the relation between the slopes of AGC1 and AGC2 PWM rates as functions of RF level is user-defined by: slope[AGC1]/slope[AGC2] = (2RATIO_A + 2RATIO_B) / 2RATIO_C.DELAGC_1Reset: 0x000x31[7:0]DELAGC_2Reset: 0x000x32[7:0]DELAGC_3Reset: 0x000x33[7:0]Confidential DELAGC_4Reset: 0x000x34[7:5][4:3][2:0] DELAGC_5Reset: 0x000x35[7:0]AGC2_THRESAGC1 PWM rate is allowed to decrease from its maximum value when the RF input level is above a take-over point defined by the fact that the PWM rate of AGC2 falls below the following threshold.AGC2_THRESH/0d255 x 100% i.e. AGC2_THRESH/0xFF x 100%.DAGC_ONIf 1, delayed AGC feature is active (AGC1 and AGC2 available for optimum tuner and IF stage gain control in application). If 0, then only AGC2 is available for gain control and ACG1 is flat. (Therefore if 0, all other bits in registers 0x30 to 0x36 are irrelevant].FRZ2_CTRL (effective only when DAGC_ON is 1)11: AGC2 is immediately frozen at its current PWM rate.10: AGC2 is definitively frozen at its current PWM rate as soon as the AGC loop locks (as flagged by signal WAGC_ACQ) and is not released until the next general reset (hard or soft).01: AGC2 is frozen at its current PWM rate as soon as the AGC loop locks but is released if the AGC loop is forced to unlock (i.e. if signal WAGC_ACQ goes back to 0).If 00: no freeze.FRZ1_CTRL (effective only when DAGC_ON is 1)11: AGC1 is immediately frozen at its current PWM rate.10: AGC1 is definitively frozen at its current PWM rate as soon as the AGC loop locks (as flagged by signal WAGC_ACQ) and is not released until the next general reset (hard or soft).01: AGC1 is frozen at its current PWM rate as soon as the AGC loop locks but is released if the AGC loop is forced to unlock (i.e if signal WAGC_ACQ goes back to 0).00: no freeze.ReservedDELAGC_6Reset: 0x000x36[7][6:5][4:3][2:0] 7346000ASTMicroelectronics Confidential23/41

Register listSTV0297

Name

DELAGC_7Reset: 0x00

Add

0x37

Bit

[7][6:4]

Signaldescription

ReservedTIME_CST

Defines the time constant of the integrator used to assess:

- the A/D overflow rate if EN_CORNER_DET is not set (register0x88 [3:0])

- the occurrence rate of corner points in the constellation if EN_CORNER_DET is set.

OVF_RATE_LO/CORNER_RATE_LOIf bit EN_CORNER_DET is cleared:

Four LSBs of OVF_RATE (unsigned 12-bit value).

The actual rate is: OVF_RATE/212. For example, if OVF_RATE = 1024, this means there is an A/D out-of-range event on average every fourth sampling.If EN_CORNER_DET is set:

Four LSBs of CORNER_RATE (unsigned 12-bit value).

The actual rate of occurrence of constellation corner points is:

CORNER_RATE/212. For example, if CORNER_RATE = 256, the average occurrence rate of constellation corner points (decided symbols) is 1/16. Read-only bits

[3:0]

DELAGC_8Reset: 0x00

0x38[7:0]OVF_RATE_HI/CORNER_RATE_HI

If EN_CORNER_DET (register 0x88 [3:0]) is cleared:Eight MSBs of OVF_RATE (unsigned 12-bit value). The actual rate is: OVF_RATE/212. For example, if OVF_RATE = 1024, this means there is an A/D out-of-range event on average every fourth sampling.Confidential If bit EN_CORNER_DET is set:The actual rate of occurrence of constellation corner points is:CORNER_RATE/212. For example, if CORNER_RATE = 256, the average occurrence rate of constellation corner points (decided symbols) is 1/16. Read-only bitsWBAGC_0

0x40[7:0]I_REFWBAGC reference. Defines the value to which the analog AGC loop tries to bring the average magnitude of the signal sampled by the A/D.

AGC2SD_LO

Eight LSBs of offset binary 10-bit value AGC2SD sent by WBAGC block to internal sigma-delta modulator to create AGC1, AGC2 and AGC12B

(i.e. AGC2SD defines the AGC PWM rates). Program its initial value so that the initial AGC level is sensible given the expected RF input level range to speed up acquisition.

Reserved

ACQ_THRESH

WBAGC is considered in lock when the rate of the AGC PWM outputs has not needed any update for 2**(ACQ_THRESH) clock cyclesSuggested value: 0xAAGC2SD_HI

Two MSBs of offset binary 10-bit value sent by WBAGC block to internal sigma delta modulator to create AGC1, AGC2 and AGC12B. See register 0x41 above.

Reset: 0x00WBAGC_1Reset: 0x00

0x41

[7:0]

WBAGC_2Reset: 0x02

0x42

[7:6][5:2]

[1:0]

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STV0297Register list

Name

WBAGC_3Reset: 0x20

Add

0x43

Bit

[7][6]

Signaldescription

ReservedWAGC_CLR

When 1, resets the WBAGC function (AGC1, AGC2, AGC12B are flat). This bit is self-clearing.WAGC_INV

Controls the sense of the WBAGC comparator.Suggested value: 1WAGC_EN

When 1 WBAGC loop is enabled, when 0 it is frozen in its current state (PWM output rates are no more allowed to change).WAGC_ACQ

WBAGC lock status (1 when locked).SWAP

Defines the ordering of the data bits out of the A/D. (If 0 sampled_if[0] is LSB, if 1 sampled_if[0] is MSB).

Test use only - normal value for STV0297 A/D: 0Reserved

ROLL_LO

Low byte of the unsigned value that controls the AGC loop response. The greater this value, the smaller the loop bandwidth.

ACQ_COUNT_LO

Low byte of the acquisition counter that checks the number of clock cycles without any AGC PWM rate update. Test use only.ACQ_COUNT_HI

High byte of the acquisition counter that checks the number of clock cycles without any PWM_OUT rate update. Test use only.

ROLL_HIHigh byte of the unsigned value that controls the AGC loop response. The greater this value, the smaller the loop bandwidth.IF_PWM_LO/NTARGET_RATE_LO

If EN_CORNER_DET = 0 (register 0x88 [3:0]), IF_PWM_LO = 8 LSBs of a signed 16-bit value encoded by the general purpose sigma-delta modulator to create the PWM signal that may be output on pin IT_PWM.

If EN_CORNER_DET = 1, NTARGET_RATE_LO defines the minimum

occurrence rate of corner points in the decoded constellations required to allow equalizer lock.

The formula to use is as follows, where OCCURRENCE_RATE (number between 0 and 1, i.e. between 0% and 100%) is the actual threshold that the user wants to set:

NTARGET_RATE [15:0] = NOT [OCCURRENCE_RATE x 2TIME_CST+9](where TIME_CST = register 0x37 [6:4])

and NTARGET_RATE_LO = NTARGET_RATE [7:0]

[5]

[4]

[3][2]

[1:0]

WBAGC_4Reset: 0x00WBAGC_5Reset: 0x00

0x45

[7:0]

0x44

[7:0]

Confidential WBAGC_6Reset: 0x00WBAGC_9Reset: 0x00

0x46[7:0]

0x49[7:0]

WBAGC_10Reset: 0x00

0x4A[7:0]WBAGC_110x4B[7:0]IF_PWM_HI/NTARGET_RATE_HI

If EN_CORNER_DET = 0 (register 0x88 [3:0]), IF_PWM_HI = 8 MSBs of a signed 16-bit value encoded by the general purpose sigma-delta modulator to create the PWM signal that may be output on pin IT_PWM.

If EN_CORNER_DET = 1, NTARGET_RATE_HI defines the minimum

occurrence rate of corner point in the decoded constellations required to allow equalizer lock. The formula to use is defined above (see register 0x4A)and NTARGET_RATE_HI = NTARGET_RATE [15:8]

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Register listSTV0297

NameAddBitSignaldescriptionSymbol timing recovery loopSTLOOP_2Reset: 0x000x52[7:5]GAIN_SCALE_PATH0With STL algorithms #1 to 3 (refer to register5B): defines the reduction factor (2GAIN_SCALE_PATH0) automatically applied to the direct gain once the symbol timing loop has acquired and is in tracking mode in order to reduce the jitter on the recovered symbol sampling instants. Causes the damping factor to decrease by 2GAIN_SCALE_PATH0 (damping factor adjustment is also affected by GAIN_SCALE_PATH1). Not used with STL algorithm #0.GAIN_SCALE_PATH1With STL algorithms #1 to 3 (refer to register0x5B): defines the reduction factor (2GAIN_SCALE_PATH1) applied to the integral gain once the symbol timing loop has acquired and is in tracking mode in order to reduce the jitter on the recovered symbol sampling instants. Causes the STL loop bandwidth to decrease by SQRT(2GAIN_SCALE_PATH1) and the damping factor to increase by this same factor (damping factor adjustment is also affected by GAIN_SCALE_PATH0). Not used with STL algorithm #0.INTEGRAL_GAIN_HIWith STL algorithms #1 to 3: MSBs of the 10-bit value coding the gain of the integral path in the timing recovery loop. The greater this value, the wider the STL loop bandwidth. Not used with STL algorithm #0.DIRECT_GAIN_LOSTL algorithm #0: LSBs of the 11-bit value that defines the gain of the direct path in the timing recovery loop.STL algorithms #1, 2, 3: bit 7 unused; bits 6 to 0 provide the 7-bit value that defines the gain of the direct path in the timing recovery loop.The greater DIRECT_GAIN, the greater the timing loop damping factor. (Damping factor is also defined by INTEGRAL_GAIN below.)SYMB_RATE_0Low byte of a 32-bit accumulator that represents the symbol timing frequency. This accumulator must be initialized by the user according to the following formula:SYMB_RATE[31:0] = 232 x (nominal symbol rate / system clock frequency).SYMB_RATE_1Second byte of a 32-bit accumulator that represents the symbol timing frequency. This accumulator must be initialized by the user according to the formula given for register 0x55.SYMB_RATE_2Third byte of a 32-bit accumulator that represents the symbol timing frequency. This accumulator must be initialized by the user according to the formula given for register 0x55.SYMB_RATE_3Most significant byte of a 32-bit accumulator that represents the symbol timing frequency. This accumulator must be initialized by the user according to the formula given for register 0x55.DIRECT_GAIN_HIMSBs of the 11-bit value that defines the gain of the direct path in the timing recovery loop for STL algorithm #0.INTEGRAL_GAIN_LODefines the gain of the integral path in the timing recovery loop. The greater this value, the wider the timing loop bandwidth and the smaller the damping factor. (Damping factor is also defined by DIRECT_GAIN above). Should not be programmed to 0x1F. Bits 1, 0 of Reg. 52 are not used with algorithm #0.Note: bits 7 to 5 are used for both DIRECT_GAIN and INTEGRAL_GAIN with STL algorithm #0.[4:2][1:0]Confidential STLOOP_3Reset: 0x000x53[7:0] STLOOP_50x55[7:0] Reset: 0x00STLOOP_6Reset: 0x000x56[7:0]STLOOP_7Reset: 0x000x57[7:0]STLOOP_8Reset: 0x000x58[7:0]STLOOP_9Reset: 0x000x59[7:5][7:0]26/41STMicroelectronics Confidential 7346000A

STV0297Register list

Name

STLOOP_10Reset: 0x00

Add

0x5A

Bit

[7][6]

Signaldescription

ReservedPHASE_EN

When 1, forces the direct path to be immediately enabled even though previous stages have not locked yet.PHASE_CLR

When 1, clears the STL accumulator, internal symbol enable pulses are no more generated. Also has the effect of freezing all blocks that work at symbol rate, in particular CRL and STL.ERR_RANGE

Can be used to saturate the timing frequency correction accumulator to ±2(ERR_RANGE+1) - 1

Should not be programmed to 0x1F. Suggested value: 0x1E.

ReservedALGOSEL

Defines the algorithm used for symbol timing recovery in the symbol timing loop:00: STL algorithm #0.01: STL algorithm #1.10: STL algorithm #2.11: STL algorithm #3.DIR

Controls the polarity of the discriminant timing.For test use only - Set to 0.EN_DIR

When 1, the timing loop includes a direct path. When 0, only the integral path has an effect

For test use only - Set to 1.ERR_CLR

When 1, clears the STL integral path.ERR_EN

When 1, forces the integral path to be immediately enabled even though the WBAGC has not fully locked yet.[5]

[4:0]

STLOOP_11Reset: 0x00

0x5B

[7:6][5:4]

[3]

[2]

Confidential [1][0]

Carrier recovery loop

CRL_0Reset: 0x00

0x60[7:0]SWEEP_LO

Low byte of a signed 12 bit frequency sweep value. The sweep operation

consists of a frequency shift (with respect to IPHASE) every symbol defined by: Fshift = (SWEEP_VALUE / 228) x Fs.

The sweep rate in Hz/s is therefore: Rsweep = (SWEEP_VALUE / 228) x FS2

CRL_1Reset: 0x00

0x61

[7][6:4]

[3:0]

ReservedGAIN_DIR

Defines the gain of the direct path in the carrier recovery loop. The greater this value, the greater the damping factor. (Damping factor is also defined by GAIN_INT below).GAIN_INT

Defines the gain of the integral path in the carrier recovery loop. The greater this value, the wider the carrier loop bandwidth and the smaller the damping factor. (Damping factor is also defined by GAIN_DIR above).

Reserved

GAIN_DIR_ADJ

Defines the reduction factor applied to the direct gain once the chip has acquired and is in tracking mode in order to reduce the jitter on the recovered carrier phase. Causes the damping factor to decrease by a factor 2GAIN_DIR_ADJ. (Damping factor adjustment is also affected by GAIN_INT_ADJ below).GAIN_INT_ADJ

Defines the reduction factor applied to the integral gain once the chip has acquired and is in tracking mode in order to reduce the jitter on the recovered carrier phase. Causes the carrier loop bandwidth to decrease by factor SQRT(2GAIN_INT_ADJ) and the damping factor to increase by this same factor. (Damping factor adjustment is also affected by GAIN_DIR_ADJ above).

CRL_2Reset: 0x06

0x62

[7:4][3:2]

[1:0]

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Register listSTV0297

Name

CRL_3Reset: 0x00CRL_4

Add

0x63

Bit

[7:0]

Signaldescription

APHASE_0

Low byte of the phase accumulator used for phase and frequency offset

compensation. Normally does not need programming. See also register 0x6B.APHASE_1

Medium byte of the phase accumulator used for phase and frequency offset compensation. Normally does not need programming. See also register 0x6B.APHASE_2

High byte of the phase accumulator used for phase and frequency offset

compensation. Normally does not need programming. See also register 0x6B.IPHASE_0

Low byte of a signed 28-bit accumulator that represents the demodulation frequency offset (after mirroring if spectral inversion is enabled, through bit SPEC_INV in register0x83). This accumulator must be programmed to its nominal value by the user according to the following formula:F_OFFSET = (IPHASE / 228) x FS [FS = symbol rate]

Important: Taken into account only on writing of register0x69.See also register 0x6B.

0x64[7:0]

CRL_50x65[7:0]

CRL_6Reset: 0x00

0x66[7:0]

CRL_70x67[7:0]

Confidential Reset: 0x00

IPHASE_1

Second byte of a signed 28-bit accumulator that represents the carrier frequency offset (after mirroring if spectral inversion is enabled, through bit SPEC_INV in register0x83). This accumulator must be programmed to its nominal value by the user according to the formula given for register0x66.Important: Taken into account only on writing of register69.See also register 0x6B.IPHASE_2Third byte of a signed 28-bit accumulator that represents the carrier frequency offset (after mirroring if spectral inversion is enabled, through bit SPEC_INV in register 0x83). This accumulator must be programmed to its nominal value by the user according to the formula given for register0x66.

Important: Taken into account only on writing of register0x69.See also register 0x6B.

SWEEP_HI

Four MSBs of a signed 12-bit frequency sweep value. The sweep operation consists of a frequency shift (with respect to IPHASE) every symbol defined by:Fshift = (SWEEP_VALUE / 228) x FS (refer to register0x60).The sweep rate in Hz/s is therefore:

CRL_8Reset: 0x00

0x68[7:0]

CRL_9Reset: 0x00

0x69

[7:4][3:0]

Rsweep = (SWEEP_VALUE / 228) x FS2iphase_3

Four MSBs of a signed 28-bit accumulator that represents the carrier frequency offset (after mirroring if spectral inversion is enabled, through bit SPEC_INV in register 0x83). This accumulator must be programmed to its nominal value by the user according to the formula given for register0x66.

Important: writing of registers0x66 to 0x68 must be followed by write access to this register.

28/41STMicroelectronics Confidential 7346000A

STV0297Register list

Name

CRL_10Reset: 0x00

Add

0x6A

Bit

[7:6][5][4][3]

Signaldescription

ReservedINT_DIS

When 1, disables the integral path of the timing recovery loop.DIR_DIS

When 1, disables the direct path of the timing recovery loop.INT_EN

When 1, forces the integral path to be immediately enabled even though previous stages have not locked yet. DIR_EN

When 1, forces the direct path to be immediately enabled even though previous stages have not locked yet.PH_EN

When 1, phase accumulator is enabled, when 0 it is frozen at its current value.SW_EN

When 1, the frequency sweep function is enabled.

CRL_SNAPSHOT

CRL status is captured in registers 0x63 to 0x68 when a dummy write is

performed at this address. Otherwise the contents of registers 0x63 to 0x68 are undetermined.

[2]

[1][0]

CRL_11Reset: 0x00

0x6B

[7:0]

Post-filter digital AGC (PMFAGC)

Confidential PMFAGC_0Reset: 0x00PMFAGC_1Reset: 0x00

0x70[7:0]

LOCK_THRESH_LO

LSBs of the value that codes the number of clock cycles after which it is assumed that the PMFAGC has locked. Suggested value: 0xFF.

PMFA_F_UNLOCKOverrides the internal PMFAGC lock status bit to unlocked.PMFA_F_LOCKOverrides the internal PMFAGC lock status bit to locked. WBAGC_F_LOCKOverrides the internal WBAGC lock status bit to locked.UP_STOP

Stops PMFAGC update, post-filter gain is stuck at its current value.Normal value: 0.LOCK_THRESH_HI

Four MSBs of the value that codes the number of clock cycles after which it is assumed that the PMFAGC has locked. Suggested value: 0x4.

PMFA_ACC0

Low byte of the unsigned 20-bit accumulator that controls the scaling performed by the PMFAGC block. Normally does not need programming.

PMFA_ACC1

Second byte of the unsigned 20-bit accumulator that controls the scaling performed by the PMFAGC block. Normally does not need programming.PMFA_LOCK_STATE

Internal flag that indicates if the PMFAGC has locked.ReservedPMFA_ACC2

Four MSBs of an unsigned 20-bit accumulator that controls the scaling performed by the PMFAGC block. Normally does not need programming.

0x71[7][6][5] PMFAGC_2Reset: 0x00PMFAGC_3Reset: 0x00PMFAGC_4Reset: 0x0C

0x740x730x72

[4][3:0]

[7:0]

[7:0]

[7][6:4][3:0]

7346000ASTMicroelectronics Confidential29/41

Register listSTV0297

NameAddBitSignaldescription

Configuration and controlCTRL_0Reset: 0x00

0x80

[7][6:4][3:1][0]

ReservedVERSIONReserved

SOFT_RESET

When 1, forces most of the chip to reset (same as grounding pin NRESET). However, blocks that can be individually reset under software control are not affected (equalizer, refer to register0x84 [0]), FEC (refer to register0x83 [4]), framing and data syncing (register0x81 [0]).

This bit is not self-clearing and can be used to put the chip in low consumption mode.

ReservedRESET_DI

When 1, resets the de-interleaver, de-interleaver sync detector and descrambler sync detector. This bit is not self-clearing.

Software interrupt register. When a bit is one, it indicates that the corresponding source has caused an exception. These bits can only be set to 1 by an exception and can only be cleared by a dummy write access to this register (soft reset does not clear them).ReservedRS_UNCORR

Reed-Solomon uncorrectable error.CORNER_LOCK

If 1, rate of occurrence of constellation corner points has exceeded user-selected threshold (set with registers 0x4B to 0x4A). Available only if bit EN_CORNER_DET is set in register0x88.EQU_LMS2Equalizer has fully converged and has entered step 2 of LMS algorithm.EQU_LMS1Equalizer has sufficiently converged and has entered step 1 of LMS algorithm.PMFAGC_IT

PMFAGC has locked. Asserted on rise of PMFA_LOCK_STATE in register0x74.WBAGC_IT

WBAGC has locked. Asserted on rise of WBAGC_ACQ in register0x43.TEST_SEL

Test mode register.

For test only: Set to 000 for normal operation.RESET_RS

When 1, resets the Reed-Solomon block. This bit is not self-clearing.SPEC_INV

Allows the demodulator to cope with any spectrum inversion possibly introduced in the transmission chain.GMAP_SEL

When 1, bit mapper module works in test mode, when 0 it works in normal mode. For test only: Set to 0 for normal operation.DFS

Input data format selection: when 1 sampled, IF data from A/D is interpreted as 2’s complement, when 0 as offset binary.

For test only: Normal value for STV0297 A/D: 0.J83C

0: ITU-J83A mode1: ITU-J83C mode.

CTRL_1Reset: 0x00

0x81

[7:1]

[0]

CTRL_2Reset: 0x00

0x82

Confidential [7:6][5][4]

[3][2] CTRL_3Reset: 0x00

0x83

[1][0][7:5]

[4][3]

[2]

[1]

[0]

30/41STMicroelectronics Confidential 7346000A

STV0297Register list

Name

CTRL_4Reset: 0x2A

Add

0x84

Bit

[7:6][5]

Signaldescription

ReservedAGC_OD

When 1, pins AGC1, AGC2 and AGC12B behave as open-drain (and pull-up can be connected to voltage up to 5.5 V), when 0 they behave as normal CMOS outputs. Reset value = 1.M_OEN

When 1, all MPEG outputs are disabled (pins are in high impedance mode).Reset value = 0.INVADCLK

Controls the polarity of the external A/D clock. Reset value = 1.CKX2DIS

When high, disables the clock doubler circuitry. Reset value = 0.CKX2SEL

Selects the clock used for MPEG serial output to be either at the same

frequency as the reference clock on pin CKEXT (when 0) or twice this frequency (when 1). Reset value = 1.RESET_EQL

When 1, clears the equalizer and also reinitializes the register 00through 04.This bit is not self-clearing. Reset value = 0.LOCKPOL

Selects the polarity of the lock indicator signal LOCK that may be output on pin IT_LOCK (0: active high, 1: active low).DI_SY_MASK

When 0, masks interrupts from de-interleaver sync detector.DI_SY_EV

Goes to 1 when de-interleaver detects a sync acquisition/loss event.DI_SY_DIR

Specifies what the event was (0: loss of sync, 1: got sync).ReservedSYNC_MSKWhen 0, masks interrupts from descrambler sync detector.SYNC_EV

Goes to 1 when descrambler detects a sync acquisition/loss event.SYNC_DIR

Specifies what the event was (0: loss of sync, 1: got sync).Bits [4] and [0] are read-only, all others are read/write.

The interrupt signal IT that may be output on pins IT_LOCK or IT_PWM is pulled low (that is, active) if:

[(DI_SY_MSK and DI_SY_EV) or (SYNC_MSK and SYNC_EV)] = 1.

The interrupt is cleared by clearing bits [5] and/or [1]. (Note that IT may also be pulled low by a channel scanning interrupt if enabled, refer to register0x24)

[4]

[3][2][1]

[0]

CTRL_5Reset: 0x00

0x85[7]

Confidential [6]

[5][4][3][2]

[1][0]

7346000ASTMicroelectronics Confidential31/41

Register listSTV0297

Name

CTRL_6Reset: 0x40

Add

0x86

Bit

[7]

Signaldescription

I2CT_EN

When 1, enables the I²C repeater for one I²C access, that is, from the end of the message that sets this bit until detection of the next stop condition on the I²C bus (so page mode is also allowed).SCLT_OD

1: pin SCLT behaves as an open-drain output and can be pulled to voltages up to 5.5V.

0: it behaves as a normal CMOS push-pull output. Reset value = 1.EXTADCLK_EN

When 1, enables generation of clock for external A/D use.

However, bit AUXCLKSEL (register0x87) must also be configured to make this clock available on pin AUXCLK. Normal / default value = 0.ITLOCKSEL

If 1, pin IT_LOCK carries interrupt signal IT. If 0, it carries lock indicator signal LOCK, unless this pin is used by three-wire bus repeater feature (refer to register0x86 bit[0]).ITPWMSEL

If 0, pin IT_PWM carries interrupt signal IT. If 1, it carries general-purpose PWM signal PWM, unless this pin is used by three-wire bus repeater feature (refer to register0x86 bit[0]).LOCKSCE

Selects the source of hardware lock indicator signal LOCK:00: lock indicator LOCK = bit SYNCSTATE. This signal is the ultimate lock flag and indicates if the full chip (including FEC and data framing) has locked. (This bit is also available by software as register0xDF, bit [7]).

01: lock indicator LOCK = bit EQU_LMS2. This signal indicates if the demodulator has firmly converged. (This information is also available by software through register0x82, bit [3]).

10: lock indicator LOCK = bit EQU_LMS1. This signal indicates if the demodulator is converging (equalizer leaves blind mode at that point). (This information is also available by software through register0x82, bit [2]).11: lock indicator LOCK = bit WAGC_ACQ indicating if analog AGC has converged. (This information is also available by software through register0x82, bit [0]).TWB_ACT

When 1, 3-wire bus repeater feature is enabled: pins IT_PWM, IT_LOCK, SCLT, SDAT, AGC12B and TWBEN_IN loose their normal functions and are forced into their 3-wire bus configuration (see pin list in the datasheet).

Bit TWB_ACT has priority over all configuration bits pertaining to these pins.SOURCESEL

SAMPLED_IF source selection.0: data comes from internal A/D.1: data comes from external source.Normal value = 0. Reset value = 1 (for production test reasons).PRGCLKDIV

Defines the division ratio used to obtain the programmable clock PRGCLK that may be output on pin AUXCLK and which is also used by some I²C repeater internal logic. The effective ratio is: 1 + PRGCLKDIV [2:0] and can therefore range from 2 to 8. (PRGCLKDIV = 0 disables the auxiliary clock).

When the I²C repeater is enabled, PRGCLKDIV should be programmed so that the period of PRGCLKDIV is slightly greater than the maximum SDAT 0-to-1 transition time.AUXCLKSEL

1: pin AUXCLK carries programmable clock PRGCLKDIV derived from CKEXT by integer division.

0: pin AUXCLK may carry a clock signal for external A/D use provided its use has been enabled through register 0x86 bit[5] (EXTADCLKEN).ReservedITLOCK_ODITPWM_OD

[6]

[5]

[4]

[3]

[2:1]

Confidential CTRL_7Reset: 0x83

87

[0]

[7]

[6:4]

[3]

[2][1][0]

32/41STMicroelectronics Confidential 7346000A

STV0297Register list

Name

CTRL_8Reset: 0x00

Add

0x88

Bit

[7]

Signaldescription

AGC12SEL

Selects which signal to output on differential AGC output pin AGC12B, if enabled (see below).AGC12B_EN

1: enables the use of pin AGC12B (differential AGC output).0: signal on pin AGC12B is flat.SIGMA_INV_1

1: inverts the polarity of signal AGC1.SIGMA_INV_2

0: inverts the polarity of signal AGC2.EN_CORNER_DET

When set, enables detection of corner points. The equalizer is only allowed to declare 1.1 ms lock and switch to decision-directed LMS algorithm when the average rate of corner points (time constant used for averaging defined through register0x37) is above a given threshold (selected through registers 0x4A and 0x4B).Spare bitsWrite to 0x0.

AUTO_QAMMODE_SEL

0: QAM mode (that is, constellation) is manually selected through register EQU_0 (0x00).

1: a state machine controlled by the bits below tries iteratively all QAM modes (16-QAM, 64-QAM, 256-QAM, 128-QAM and finally 32-QAM).AUTOCONSTEL_TIMER

Defines the time spent in each QAM mode tried as:AUTOCONSTEL_TIMER x 213 x Ts (where Ts is the symbol duration).AUTOSTOP_CONSTELIf 1, the state machine stops automatically and stays in its current QAM mode upon detection of full equalizer lock.AUTOCONSTEL_ONSetting this bit to 1 starts the QAM mode state machine. Setting it to 0 stops the state machine, and the chip stays in its current QAM mode.Reserved

[6]

[5][4][3]

[2:0]

CTRL_9Reset: 0x00

0x89

[7]

Confidential [6:3]

[2]

[1] [0]

De-interleaver sync detector

DEINT_SYNC_0

0x90[7][6]

Reset: 0x01

[5:4]

[3:2]

[1:0]

DI_UNLOCK

When 1, forces the de-interleaver sync detector to unlock. Normal value: 0.DI_FREEZE

When 1, freezes the de-interleaver sync detector in locked mode.Normal value: 0.MISMATCH

Indicates the number of bit mismatches in a sync byte allowed during track state (more erroneous bits and the byte is regarded as mismatching).ACQ_MODE

Defines the number of states required to declare acquisition:

The de-interleaver sync detector declares an acquisition and enters tracking when it has detected at least (ACQ_MODE + 3) successive correct sync bytes, out of which one must be the inverted sync byte.TRKMODE

Defines the number of states (number of successive mismatching sync bytes) required to unlock:

TRK_MODE + 1 correct sync bytes are required.

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Register listSTV0297

Name

DEINT_SYNC_1

Add

0x91

Bit

[7:6][5]

Signaldescription

ReservedSYNLOST

Goes to 1 when the de-interleaver looses sync (even if it is forced to stay in locked state by bit DI_FREEZE in register0x90). (Cleared in case of relocking).SMCNTR

Increases each time the detected sync byte matches, decreases each time it mismatches. Saturates at 0 and (ACQ_MODE + 2). For test only.SYNCSTATE

Current state of the sync state machine. For test only. Read-only bits

Reset: 0x01

[4:2]

[1:0]

Integrated BER testerBERT_0Reset: 0x00

0xA0

[7]

[6:5][4][3]

Confidential [2:0]

BERT_ON

Set to 1 to start counting bit/byte errors (before R/S correction).

If ERR_MODE = 0 (see below), BERT_ON is automatically reset to 0 when the number of data bytes programmed through NBYTE (see below) has elapsed. If ERR_MODE = 1, it is not automatically reset.Reserved

ERR_SOURCE0: count bit errors,1: count byte errors.ERR_MODE

0: the internal error counter stops automatically when the number of bytes defined by NBYTE has elapsed.

1: it does not stop automatically, NBYTE is ignored and BERT_ON must be explicitly cleared by the user to stop the error counter.NBYTE

Defines the number of data bytes during which bit/byte errors are to be detected as 2(2.NBYTE + 12). (Used only if ERR_MODE = 0).(So the count period can range from 4096 to 226 bytes).

BERT_1Reset: 0x00

0xA1[7:0]

ERRCOUNT_LOInternal byte/bit error counter, low byte. Note that this result is the raw bit/byte error count and includes any error falling within the R/S redundancy bytes.ERRCOUNT_HI

Internal byte/bit error counter, high byte. Note that this result is the raw bit/byte error count and includes any error falling within the R/S redundancy bytes.

BERT_2Reset: 0x00De-interleaverDEINT_0Reset: 0x91

0xA2[7:0]

0xB0[7][6][5][4:0]

USEINT

Must be left at 1 (default).DAVIC

Selects DAVIC mapping. Reset value = 0 (ITU J83 A&C mapping).ReservedM

Interleaving depth parameter. Default = 0d17, OK for ITU J83-A&C. Write to 1 and set depth (register0xB1) to 0 to bypass de-interleaver.

DEPTH

De-interleaver depth - 1. Default = 0d11, OK for ITU J83-A&C. Write to 0 and set M (register0xB0) to 0 to bypass de-interleaver.ReservedReserved

DEINT_1Reset: 0x0BDEINT_2DEINT_3

0xB1[7:0]

0xB20xB3

34/41STMicroelectronics Confidential 7346000A

STV0297Register list

Name

Output formatterOUTFORMAT_0Reset: 0x53

AddBitSignaldescription

0xC0

[7][6]

[5]

[4]

[3]

[2][1]

[0]

ReservedREFRESH47

If 1, inverted MPEG sync bytes are reinverted from 0xB8 back to 0x47. Reset value: 1. Do not set to 0.BE_BYPASS

When 1, all back-end stages, that is, those following symbol-to-byte(de-interleaving, R/S, descrambler), are bypassed. Reset value: 0.CKOUTPAR

Selects polarity of M_CKOUT when common-interface format is disabled (Figure7A to Figure8B). Reset value: 1.CT_NBST

When high all MPEG/TS bits are output, else R/S parity is discarded.Reset value: 0.S_NP

Selects serial (if 1) or parallel (if 0) interface. Reset value: 0.TEI_ENA

When high, enables setting of MPEG-2 TEI bit in case of uncorrectable packet error. Reset value: 1.DS_ENA

When high, descrambling is enabled. Reset / normal value: 1.SYNC_STRIP

When 1, the sync word at the head of MPEG/TS packets is stripped off (corresponding M_VAL pulse is suppressed).CI_EN

DVB CA common interface enable. When 1, the MPEG/TS output interface conforms to the DVB common-interface specification. When 0, the interface is ST’s parallel or serial format as indicated by register0xC0.CICLK_POLSelects the polarity of the common interface clock supplied on pin M_CKOUT. Common interface control signals toggle on M_CKOUT rising edge if 0, or on falling edge if 1.CICLK_BASE

Selects the base clock used to generate the common interface clock. If 1, factors N1 and N2 defined in register 0xC2 apply to the system clock (for example, 28.8MHz). If 0, they apply to the internally-generated double frequency clock (for example, 57.6 MHz) enabled by bit CKX2DIS in register0x84.Reserved

Reserved

CI_DIVRANGE

Defines the division ratio N between the base clock (defined in register0xC1) and the common-interface clock M_CKOUT: N = N1 + N2

where N1 = CI_DIVRANGE[5:3] and N2 = CI_DIVRANGE[2:0].

N1 represents the number of base clock cycles during which M_CKOUT is high, N2 is the number of base clock cycles during which M_CKOUT is low.

Polarity given for CICLK_POL in register 0xC1 = 0, opposite result if this bit is 1.Resulting M_CKOUT frequency = base clock frequency / N.Duty cycle ratio depends on the ratio N1/N2 (50% if N1 = N2).

Confidential OUTFORMAT_1Reset: 0x10

0xC1[7]

[6]

[5]

OUTFORMAT_2Reset: 0x24

0xC2

[4]

[3:0][7:6][5:0]

Reed-Solomon decoder, Descrambler sync detector, DescramblerRS_DESC_0Reset: 0x00RS_DESC_1Reset: 0x00

0xD1

[7:0]

0xD0

[7:0]

BK_CT_LO

Low byte of the block counter (counting the number of MPEG-TS packets elapsed since the block counters were enabled. Refer to register0xDF bit [0]).BK_CT_HI

High byte of the block counter (counting the number of MPEG-TS packets elapsed since the block counters were enabled. Refer to register0xDF bit [0]).

7346000ASTMicroelectronics Confidential35/41

Register listSTV0297

Name

RS_DESC_2Reset: 0x00

Add

0xD2

Bit

[7:0]

Signaldescription

CORR_CT_LO

Low byte of the corrected block counter (counts the number of MPEG-TS

packets that were R/S corrected since the block counters were enabled. Refer to register0xDF bit [0]).

CORR_CT_HI

High byte of the corrected block counter (counts the number of MPEG-TS

packets that were R/S corrected since the block counters were enabled. Refer to register0xDF bit [0]).

UNCORR_CT_LO

Low byte of the uncorrected block counter (counts packets that were detected as erroneous by the R/S but not correctable).

UNCORR_CT_HI

High byte of the uncorrected block counter (counts packets that were detected as erroneous by the R/S but not correctable).

Reserved

DIS_UNLOCK

Disables the capability of the de-interleaver sync detector to switch the descrambler sync detector to unlocked mode. Normal value: 0.MODE

Defines the descrambler sync state machine tracking operation. This machine has two states: acquisition and tracking. The current state conditions the operation of MPEG-TS output pins and is reflected in bit SYNCSTATE of register 0xDF (see below).00: Descrambler sync detector cares only for inverted sync byte. If it is found at the expected time, it goes to tracking, if not it goes to acquisition.10: Complete tracking mode. Descrambler sync detector cares only for inverted sync bytes to lock, but checks all sync bytes (inverted or not) once in tracking state; if one of them is wrong, it goes back to acquisition.X1: Freeze mode. Once locked, the de-interleaver sync detector stays in tracking state (MPEG output pins stay active) even if there is a missing sync byte.

RS_DESC_3Reset: 0x00

0xD3[7:0]

RS_DESC_4Reset: 0x00RS_DESC_5Reset: 0x00RS_DESC_14Reset: 0x00

0xD4[7:0]

0xD5[7:0]

0xDE

[7:3][2]

[1:0]

Confidential RS_DESC_15Reset: 0x00

0xDF[7]

[6:3][2]

[1]

[0]

SYNCSTATE1: tracking,0: trying to acquire.

This is the ultimate lock flag. It reflects the state of the descrambler sync

detector (although this state can be forced by means of register 0xDE). Only if the state is tracking are MPEG/TS output pins M_** active (if not, they are stuck at 0).

ReservedRS_NOCORR

When 1, the Reed-Solomon block does not correct any errors, but all of its other functions operate normally.

When 0, the R/S operates normally (default).CT_HOLD

When 1 the block counters described in registers 0xD0 to 0xD5 are prevented from being updated, when 0 they can be updated.CT_CLEAR

0: the block counters described in registers 0xD0 to 0xD5 are cleared.1: the block counters described in registers 0xD0 to 0xD5 are enabled.

36/41STMicroelectronics Confidential 7346000A

STV0297Electrical characteristics

5Electrical characteristics

Table 2: Absolute maximum ratings1SymbolVDDV5VTVINToperTstgParameterDC supply voltageVoltage on 5 V tolerant pinsVoltage on input pinsOperating ambient temperatureStorage temperatureValue-0.5, +4.0-0.5, +5.5-0.5, VDD+ 0.50, +70-40, +150UnitVVV°C°C1.These are maximum limits. Exceeding them may result in permanent damage to the device. Operation at these limits is not intended.Table 3: DC electrical characteristicsSymbolVDDVILVIHVOLVOHParameterDC supply voltageInput logic lowInput logic highOutput logic lowOutput logic highMin.3.02.0Typ.3.3Max.3.60.80.4UnitVVVVVConfidential 2.4 Table 4: AD10 characteristics (values valid for sampling rate up to 36 MHz)SymbolDLEILEENOBTHDSNDVINParameterDifferential linearity errorIntegral linearity errorEffective number of bitsTotal harmonic distortionSignal-to-noise ratio with distortionRecommended input swingMin.Typ.+/-0.5+/-1.08.5-50500.5 to 1.5Max.UnitLSBLSBbitsdBdBV Table 5: AC electrical characteristics (Tamb=25 °C, VDD = 3.3 V unless otherwise specified)SymbolFclkTclkTrstFscl1TI2Cpulse1Tprop2Tckx2pulseIdd_core3Idd_pads3Idd_a4ParameterSystem clock frequencySystem clock periodHardware reset durationI²C data rateSCL and SDA high and low level state durationDigital outputs propagation time w.r.t. CKEXT rising edgeHigh and low level duration of serial TS clock generated by internal frequency doublerDigital core current consumptionPads current consumptionA/D current consumptionMin.27.710Typ.Max.36UnitMHznsTclkFclk/168.Tclk212Tclk/210011251301235MHznsnsnsmAmAmA1.I²C data rate is limited to 400 kHz/s for I²C messages intended to be repeated to the tuner on the private I²C bus (SCLT, SDAT).2.Cload ~80 pF.

3.Measured in the following conditions: Fs = 9 Msymb/s, Fclk = 36 MHz, VDD = 3.6 V, Cload ~ 80 pF.4.With A/D clocked at 36 MHz.

7346000ASTMicroelectronics Confidential37/41

ApplicationsSTV0297

6Applications

Figure 14: Typical application diagram

RF inLow-pass filterAnalog gain control signalCable tunerIF (36 MHz or 7.2 Mhz typical)PWM signalSAW filterLow-pass filterIF amplifierAnalog gain control signalPWM signalConfidential PrivateI²C busLevel shifter(1 V DC) STV029730SCLT29SDATI²C bus28SCL27SDA64IT_PWM6IT_LOCKM_CKOUT14M_SYNC25M_ERR10M_VAL15M_DATA[7:0](pins 23 to 16)XTAL250A/D converterAGC233AGC132Digital coreCKEXT49Quartzcrystal MicrocontrollerDVB conditional access moduleorPacket demultiplexer/transport IC(for example, ST20-TPx or STi55xx or STV0191)38/41STMicroelectronics Confidential 7346000A

STV0297

Figure 15: Application diagram: A/D connections

Applications

VDDASTV0297VDDAVDDA_SHIELDVDDAVRHFR ladder~440 ohms47pFGNDA2.2µF1.5V47pFGNDA47pFGNDA10k2.2ÿFVCC47pF10kGNDA2.2µF15pF2.2µF0.5VRbot~220 ohmsVRLFVCCAAnalog IF from Tuner50 ohm2.2 nF1V DCANAINDANAIN+-300 ohm (typ.,IF source dependent)GNDAGNDA1Confidential GNDARGND GNDAGNDA2 GNDAVSSA_SHIELD Voltageregulator 1.5 Vor:VCC (3.3V) - Need excellent AC filteringRtop ~800 ohms1.5 VRladder +Rbot ~660 ohmsGNDANote:1For best performance, the impedance seen on ANAIN and ANAIND (pseudo-differential input)

should be matched.

2It is strongly recommended that a separate analog ground plane is used on the board.

7346000ASTMicroelectronics Confidential39/41

Package mechanical dataSTV0297

7Package mechanical data

Figure 16: STV0297 package diagram (TQFP64: 64-pin full plastic quad flat pack)

AA264e49A10,10 mm.004 inchSEATING PLANE1481633Confidential E3E1E17 L1 D3D1D32L K0,25 mm.010 inchGAGE PLANETable 6: STV0297 package dimensions

Millimeters

Dimension

AA1A2BCDD1D3eEE1E3LL1

0.450.051.350.170.09

12.0010.007.500.5012.0010.007.500.601.00

0.75

0.018

1

1.400.22

Inches

Typ.

Max.

1.600.151.450.270.20

0.0020.0530.0070.004

0.4720.3940.2950.01970.4720.3940.2950.0240.039

0.030

0.0550.009

Min.Min.Typ.

BcMax.

0.0630.0060.0570.0110.008

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