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LM5105资料

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LM5105100VHalfBridgeGateDriverwithProgrammableDead-timeFebruary2005

LM5105

100VHalfBridgeGateDriverwithProgrammableDead-time

GeneralDescription

TheLM5105isahighvoltagegatedriverdesignedtodriveboththehighsideandlowsideN–ChannelMOSFETsinasynchronousbuckorhalfbridgeconfiguration.Thefloatinghigh-sidedriveriscapableofworkingwithrailvoltagesupto100V.ThesinglecontrolinputiscompatiblewithTTLsignallevelsandasingleexternalresistorprogramstheswitchingtransitiondead-timethroughtightlymatchedturn-ondelaycircuits.Ahighvoltagediodeisprovidedtochargethehighsidegatedrivebootstrapcapacitor.Therobustlevelshifttechnologyoperatesathighspeedwhileconsuminglowpowerandprovidescleanoutputtransitions.Under-voltagelockoutdisablesthegatedriverwheneitherthelowsideorthebootstrappedhighsidesupplyvoltageisbelowtheop-eratingthreshold.TheLM5105isofferedinthethermallyenhanced10-pinLLPplasticpackage.

nnnnnnnnnn

1.8Apeakgatedrivecurrent

Bootstrapsupplyvoltagerangeupto118VDCIntegratedbootstrapdiodeSingleTTLcompatibleInput

Programmableturn-ondelays(Dead-time)EnableInputpin

Fastturn-offpropagationdelays(26nstypical)Drives1000pFwith15nsriseandfalltimeSupplyrailunder-voltagelockoutLowpowerconsumption

TypicalApplications

nSolidStatemotordrives

nHalfandFullBridgepowerconvertersnTwoswitchforwardpowerconverters

Features

nDrivesbothahighsideandlowsideN-channelMOSFET

Package

nLLP-10(4mmx4mm)

SimplifiedBlockDiagram

20137502

FIGURE1.

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LM5105ConnectionDiagram

20137501

10-LeadLLP

SeeNSNumberSDC10A

OrderingInformation

OrderingNumberLM5105SDLM5105SDX

PackageType

LLP-10LLP-10

NSCPackageDrawing

SDC10ASDC10A

SuppliedAs

1000shippedasTape&Reel4500shippedasTape&Reel

PinDescriptions

Pin12

NameVDDHB

Description

PositivegatedrivesupplyHighsidegatedriverbootstraprailHighsidegatedriveroutput

HighsideMOSFETsourceconnectionNotConnected

Deadtimeprogrammingpin

AresistorfromRDTtoVSSprogramstheturn-ondelayofboththehighandlowsideMOSFETs.TheresistorshouldbeplacedclosetotheICtominimizenoisecouplingfromadjacentPCboardtraces.TTLcompatiblethresholdwithhysteresis.LOandHOareheldinthelowstatewhenENislow.

TTLcompatiblethresholdwithhysteresis.ThehighsideMOSFETisturnedonandthelowsideMOSFETturnedoffwhenINishigh.Allsignalsarereferencedtothisground.

ConnecttothegateofthelowsideN-MOSdevicewithashort,lowinductancepath.

ApplicationInformation

DecoupleVDDtoVSSusingalowESR/ESLcapacitor,placedasclosetotheICaspossible.

ConnectthepositiveterminalofbootstrapcapacitortotheHBpinandconnectnegativeterminaltoHS.TheBootstrapcapacitorshouldbeplacedasclosetoICaspossible.

ConnecttothegateofhighsideN-MOSdevicethroughashort,lowinductancepath.

ConnecttothenegativeterminalofthebootststrapcapacitorandtothesourceofthehighsideN-MOSdevice.

3456

HOHSNCRDT

78910

ENINVSSLO

LogicinputfordriverDisable/Enable

LogicinputforgatedriverGroundreturn

Lowsidegatedriveroutput

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LM5105AbsoluteMaximumRatings(Note1)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.VDDtoVSSHBtoHSINandENtoVSSLOtoVSSHOtoVSSHStoVSS(Note6)HBtoVSSRDTtoVSSJunctionTemperature

–0.3Vto+18V–0.3Vto+18V–0.3VtoVDD+0.3V–0.3VtoVDD+0.3VHS–0.3VtoHB+0.3V

−5Vto+100V

118V

–0.3Vto5V

+150˚C

StorageTemperatureRangeESDRatingHBM(Note2)

–55˚Cto+150˚C

2kV

RecommendedOperatingConditions

VDDHS(Note6)HB

HSSlewRateJunctionTemperature

+8Vto+14V–1Vto100V

HS+8VtoHS+14V

<50V/ns

–40˚Cto+125˚C

SpecificationsinstandardtypefaceareforTJ=+25˚C,andthoseinboldface

typeapplyoverthefulloperatingjunctiontemperaturerange.Unlessotherwisespecified,VDD=HB=12V,VSS=HS=0V,EN=5V.NoloadonLOorHO.RDT=100kΩ(Note4).Symbol

SUPPLYCURRENTSIDDIDDOIHBIHBOIHBSIHBSOVILVIHRpdVRDTIRDTVDDRVDDHVHBRVHBHVDLVDHRDVOLLVOHLIOHLIOLLVOLHVOHHIOHHVDDQuiescentCurrentVDDOperatingCurrentTotalHBQuiescentCurrentTotalHBOperatingCurrentHBtoVSSCurrent,QuiescentHBtoVSSCurrent,OperatingLowLevelInputVoltageThresholdHighLevelInputVoltageThresholdInputPulldownResistancePinINandENNominalVoltageatRDTRDTPinCurrentLimitVDDRisingThresholdVDDThresholdHysteresisHBRisingThresholdHBThresholdHysteresisLow-CurrentForwardVoltageHigh-CurrentForwardVoltageDynamicResistanceLow-LevelOutputVoltageHigh-LevelOutputVoltagePeakPullupCurrentPeakPulldownCurrentLow-LevelOutputVoltageHigh-LevelOutputVoltagePeakPullupCurrent

IVDD-HB=100µAIVDD-HB=100mAIVDD-HB=100mAILO=100mAILO=–100mA,VOHL=VDD–VLOLO=0VLO=12VIHO=100mAIHO=–100mA,VOHH=HB–HOHO=0V

5.7

RDT=0V

1002.70.756.0

IN=EN=0Vf=500kHzIN=EN=0Vf=500kHzHS=HB=100Vf=500kHz

0.8

0.341.650.061.30.050.11.81.820031.56.90.56.60.40.60.850.80.250.351.81.60.250.351.8

0.40.550.91.11.50.40.557.12.25003.32.257.40.630.2310

mAmAmAmAµAmAVVkΩVmAVVVVVVΩVVAAVVA

Parameter

Conditions

Min

Typ

Max

Units

ElectricalCharacteristics

INPUTINandEN

DEAD-TIMECONTROLS

UNDERVOLTAGEPROTECTION

BOOTSTRAPDIODE

LOGATEDRIVER

HOGATEDRIVER

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LM5105ElectricalCharacteristicsSpecificationsinstandardtypefaceareforTJ=+25˚C,andthoseinboldfacetype

applyoverthefulloperatingjunctiontemperaturerange.Unlessotherwisespecified,VDD=HB=12V,VSS=HS=0V,EN=5V.NoloadonLOorHO.RDT=100kΩ(Note4).(Continued)SymbolIOLHθJATHERMALRESISTANCE

JunctiontoAmbient

(Note3),(Note5)

40

˚C/W

Parameter

PeakPulldownCurrent

Conditions

HO=12V

Min

Typ1.6

Max

UnitsA

SpecificationsinstandardtypefaceareforTJ=+25˚C,andthoseinboldface

typeapplyoverthefulloperatingjunctiontemperaturerange.Unlessotherwisespecified,VDD=HB=12V,VSS=HS=0V,NoLoadonLOorHO(Note4).SymboltLPHLtHPHLtLPLHtHPLHtLPLHtHPLHten,tsdDT1,DT2MDTtR,tFtBSParameter

LowerTurn-OffPropagationDelayUpperTurn-OffPropagationDelayLowerTurn-OnPropagationDelayUpperTurn-OnPropagationDelayLowerTurn-OnPropagationDelayUpperTurn-OnPropagationDelayEnableandShutdownpropagationdelayDead-timeLOOFFtoHOON&HOOFFtoLOON

Dead-timematchingEitherOutputRise/FallTime

BootstrapDiodeTurn-OnorTurn-OffTime

RDT=100kRDT=10kRDT=100kCL=1000pF

IF=20mA,IR=200mARDT=100kRDT=100kRDT=10kRDT=10k

4854857575

Conditions

Min

Typ26265955951051052857080501550

ns

Max5656705705150150

Unitsnsnsnsnsnsnsnsµs

SwitchingCharacteristics

Note1:AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothecomponentmayoccur.OperatingRatingsareconditionsunderwhichoperationofthedeviceisguaranteed.OperatingRatingsdonotimplyguaranteedperformancelimits.Forguaranteedperformancelimitsandassociatedtestconditions,seetheElectricalCharacteristicstables.

Note2:Thehumanbodymodelisa100pFcapacitordischargedthrougha1.5kΩresistorintoeachpin.Pin2,Pin3andPin4areratedat500V.

Note3:4layerboardwithCufinishedthickness1.5/1.0/1.0/1.5oz.Maximumdiesizeused.5xbodylengthofCutraceonPCBtop.50x50mmgroundandpowerplanesembeddedinPCB.SeeApplicationNoteAN-1187.

Note4:MinandMaxlimitsare100%productiontestedat25˚C.LimitsovertheoperatingtemperaturerangeareguaranteedthroughcorrelationusingStatisticalQualityControl(SQC)methods.LimitsareusedtocalculateNational’sAverageOutgoingQualityLevel(AOQL).

Note5:TheθJAisnotaconstantforthepackageanddependsontheprintedcircuitboarddesignandtheoperatingconditions.

Note6:IntheapplicationtheHSnodeisclampedbythebodydiodeoftheexternallowerN-MOSFET,thereforetheHSvoltagewillgenerallynotexceed-1V.Howeverinsomeapplications,boardresistanceandinductancemayresultintheHSnodeexceedingthisstatedvoltagetransiently.

IfnegativetransientsoccuronHS,theHSvoltagemustneverbemorenegativethanVDD-15V.Forexample,ifVDD=10V,thenegativetransientsatHSmustnotexceed-5V.

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LM5105TypicalPerformanceCharacteristics

VDDOperatingCurrentvsFrequency

OperatingCurrentvsTemperature

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20137511

QuiescentCurrentvsSupplyVoltageQuiescentCurrentvsTemperature

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20137513

HBOperatingCurrentvsFrequencyHO&LOPeakOutputCurrentvsOutputVoltage

20137516

20137517

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LM5105TypicalPerformanceCharacteristics

DiodeForwardVoltage

(Continued)

UndervoltageHysteresisvsTemperature

20137515

20137518

UndervoltageRisingThresholdvsTemperatureLO&HO-HighLevelOutputVoltagevsTemperature

2013751920137520

LO&HO-LowLevelOutputVoltagevsTemperatureInputThresholdvsTemperature

2013752120137522

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LM5105TypicalPerformanceCharacteristics

Dead-TimevsRTResistorValue

(Continued)

Dead-TimevsTemperature(RT=10k)

20137514

20137526

Dead-TimevsTemperature(RT=100k)

20137527

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LM5105TimingDiagrams

20137503

LM5105Input-OutputWaveforms

FIGURE2.

20137504

LM5105SwitchingTimeDefinitions:tLPLH,tLPHL,tHPLH,tHPHLFIGURE3.

OperationalNotes

TheLM5105isasinglePWMinputGateDriverwithEnablethatoffersaprogrammabledeadtime.ThedeadtimeissetwitharesistorattheRDTpinandcanbeadjustedfrom100nsto600ns.ThewidedeadtimeprogrammingrangeprovidestheflexibilitytooptimizedrivesignaltimingforawiderangeofMOSFETSandapplications.

TheRDTpinisbiasedat3Vandcurrentlimitedto1mAmaximumprogrammingcurrent.Thetimedelaygeneratorwillaccommodateresistorvaluesfrom5kto100kwithadeadtimetimethatisproportionaltotheRDTresistance.GroundingtheRDTpinprogramstheLM5105todrivebothoutputswithminimumdeadtime.

STARTUPANDUVLO

Bothtopandbottomdriversincludeunder-voltagelockout(UVLO)protectioncircuitrywhichmonitorsthesupplyvolt-age(VDD)andbootstrapcapacitorvoltage(HB–HS)inde-pendently.TheUVLOcircuitinhibitseachdriveruntilsuffi-cientsupplyvoltageisavailabletoturn-ontheexternalMOSFETs,andtheUVLOhysteresispreventschatteringduringsupplyvoltagetransitions.WhenthesupplyvoltageisappliedtotheVDDpinofLM5105,thetopandbottomgatesareheldlowuntilVDDexceedstheUVLOthreshold,typicallyabout6.9V.AnyUVLOconditiononthebootstrapcapacitorwilldisableonlythehighsideoutput(HO).

20137530

LM5105Enable:tsdFIGURE4.

20137531

LM5105Dead-time:DT

FIGURE5.

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LM5105OperationalNotes

LAYOUTCONSIDERATIONS

(Continued)

POWERDISSIPATIONCONSIDERATIONS

ThetotalICpowerdissipationisthesumofthegatedriverlossesandthebootstrapdiodelosses.Thegatedriverlossesarerelatedtotheswitchingfrequency(f),outputloadcapacitanceonLOandHO(CL),andsupplyvoltage(VDD)andcanberoughlycalculatedas:

PDGATES=2•f•CL•VDD2TherearesomeadditionallossesinthegatedriversduetotheinternalCMOSstagesusedtobuffertheLOandHOoutputs.Thefollowingplotshowsthemeasuredgatedriverpowerdissipationversusfrequencyandloadcapacitance.Athigherfrequenciesandloadcapacitancevalues,thepowerdissipationisdominatedbythepowerlossesdrivingtheoutputloadsandagreeswellwiththeaboveequation.Thisplotcanbeusedtoapproximatethepowerlossesduetothegatedrivers.

GateDriverPowerDissipation(LO+HO)VCC=12V,NeglectingDiodeLosses

Theoptimumperformanceofhighandlowsidegatedriverscannotbeachievedwithouttakingdueconsiderationsduringcircuitboardlayout.Followingpointsareemphasized.1.

AlowESR/ESLcapacitormustbeconnectedclosetotheIC,andbetweenVDDandVSSpinsandbetweenHBandHSpinstosupporthighpeakcurrentsbeingdrawnfromVDDduringturn-onoftheexternalMOSFET.

2.Topreventlargevoltagetransientsatthedrainofthetop

MOSFET,alowESRelectrolyticcapacitormustbecon-nectedbetweenMOSFETdrainandground(VSS).3.

Inordertoavoidlargenegativetransientsontheswitchnode(HS)pin,theparasiticinductancesinthesourceoftopMOSFETandinthedrainofthebottomMOSFET(synchronousrectifier)mustbeminimized.

Groundingconsiderations:

a)ThefirstpriorityindesigninggroundingconnectionsistoconfinethehighpeakcurrentsfromcharginganddischargingtheMOSFETgateinaminimalphysicalarea.Thiswilldecreasetheloopinductanceandmini-mizenoiseissuesonthegateterminaloftheMOSFET.TheMOSFETsshouldbeplacedascloseaspossibletothegatedriver.

b)Thesecondhighcurrentpathincludesthebootstrapcapacitor,thebootstrapdiode,thelocalgroundrefer-encedbypasscapacitorandlowsideMOSFETbodydiode.Thebootstrapcapacitorisrechargedonthecycle-by-cyclebasisthroughthebootstrapdiodefromthegroundreferencedVDDbypasscapacitor.There-chargingoccursinashorttimeintervalandinvolveshighpeakcurrent.Minimizingthislooplengthandareaonthecircuitboardisimportanttoensurereliableoperation.TheresistorontheRDTpinmustbeplacedveryclosetotheICandseperatedfromhighcurrentpathstoavoidnoisecouplingtothetimedelaygeneratorwhichcoulddisrupttimeroperation.

4.

5.

20137505

Thebootstrapdiodepowerlossisthesumoftheforwardbiaspowerlossthatoccurswhilechargingthebootstrapcapacitorandthereversebiaspowerlossthatoccursduringreverserecovery.Sinceeachoftheseeventshappensoncepercycle,thediodepowerlossisproportionaltofrequency.Largercapacitiveloadsrequiremorecurrenttorechargethebootstrapcapacitorresultinginmorelosses.Higherinputvoltages(VIN)tothehalfbridgeresultinhigherreverserecoverylosses.Thefollowingplotwasgeneratedbasedoncalculationsandlabmeasurementsofthedioderecoverytimeandcurrentunderseveraloperatingconditions.Thiscanbeusefulforapproximatingthediodepowerdissipation.

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LM5105OperationalNotes

(Continued)

DiodePowerDissipationVIN=80V

ThetotalICpowerdissipationcanbeestimatedfromtheaboveplotsbysummingthegatedrivelosseswiththebootstrapdiodelossesfortheintendedapplication.Becausethediodelossescanbesignificant,anexternaldiodeplacedinparallelwiththeinternalbootstrapdiode(refertoFigure6)andcanbehelpfulinremovingpowerfromtheIC.Forthistobeeffective,theexternaldiodemustbeplacedclosetotheICtominimizeseriesinductanceandhaveasignificantlylowerforwardvoltagedropthantheinternaldiode.HSTransientVoltagesBelowGround

TheHSnodewillalwaysbeclampedbythebodydiodeofthelowerexternalFET.Insomesituations,boardresis-tancesandinductancescancausetheHSnodetotran-sientlyswingseveralvoltsbelowground.TheHSnodecanswingbelowgroundprovided:1.

HSmustalwaysbeatalowerpotentialthanHO.PullingHOmorethan-0.3VbelowHScanactivateparasitictransistorsresultinginexcessivecurrenttoflowfromtheHBsupplypossiblyresultingindamagetotheIC.ThesamerelationshipistruewithLOandVSS.Ifnecessary,aSchottkydiodecanbeplacedexternallybetweenHOandHSorLOandGNDtoprotecttheICfromthistypeoftransient.ThediodemustbeplacedasclosetotheICpinsaspossibleinordertobeeffective.

2.HBtoHSoperatingvoltageshouldbe15Vorless.

Hence,iftheHSpintransientvoltageis-5V,VDDshouldbeideallylimitedto10VtokeepHBtoHSbelow15V.3.AlowESRbypasscapacitorbetweenHBtoHSaswell

asVCCtoVSSisessentialforproperoperation.ThecapacitorshouldbelocatedattheleadsoftheICtominimizeseriesinductance.ThepeakcurrentsfromLOandHOcanbequitelarge.AnyseriesinductanceswiththebypasscapacitorwillcausevoltageringingattheleadsoftheICwhichmustbeavoidedforreliableop-eration.

20137506

DiodePowerDissipationVIN=40V

20137507

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LM5105OperationalNotes

(Continued)

LM5105DrivingMOSFETsConnectedinHalf-BridgeConfiguration

20137508

FIGURE6.

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LM5105100VHalfBridgeGateDriverwithProgrammableDead-timePhysicalDimensions

inches(millimeters)unlessotherwisenoted

Notes:Unlessotherwisespecified

1.2.3.

Standardleadfinishtobe200microinches/5.00micrometersminimumtin/lead(solder)oncopper.Pin1identificationtohavehalfoffullcircleoption.NoJEDECregistrationasofFeb.2000.

LLP-10OutlineDrawingNSPackageNumberSDC10A

Nationaldoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandNationalreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecifications.Forthemostcurrentproductinformationvisitusatwww.national.com.LIFESUPPORTPOLICY

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