SI3036资料

2020-09-29 来源：易榕旅网

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Si3035

3.3V FCC/JATE DIRECT ACCESS ARRANGEMENT

FeaturesComplete DAA includes the following:!!!!!!

3.3V to 5V Digital/Analog Power SuppliesJATE Filter Option86 dB Dynamic Range TX/RX PathsDaisy-Chaining for Up to Eight DevicesIntegrated Ring Detector3000 V Isolation!!!!!!!!!Support for Caller IDLow Profile SOIC PackagesDirect Interface to DSPsIntegrated Modem CodecCompliant with FCC Part 68Low-Power Standby ModeProprietary ISOcap™ TechnologyPin Compatible with Si3034, Si3032Optional IIR Digital FilterOrdering InformationSee page50.Applications!!Pin AssignmentsSi3021 (SOIC)!!V.90 ModemsVoice Mail SystemsFax MachinesSet Top BoxesMCLKFSYNCSCLKVDSDOSDIFC/RGDTRESET12345678161514131211109OFHKRGDT/FSDM0VAGNDC1AM1AOUTDescriptionThe Si3035 is an integrated direct access arrangement (DAA) chipset thatprovides a digital, low-cost, solid-state interface to a telephone line.Available in two 16-pin small outline packages, it eliminates the need for ananalog front end (AFE), an isolation transformer, relays, opto-isolators, anda 2- to 4-wire hybrid. The Si3035 dramatically reduces the number ofdiscrete components and cost required to achieve compliance with FCCPart 68. The Si3035 interfaces directly to standard modem DSPs andsupports all FCC and JATE out-of-band noise requirements. Internationalsupport is provided by the pin compatible Si3034. Si3021 (TSSOP)SDOSDIFC/RGDTRESETAOUTM1C1AGND12345678161514131211109VDSCLKFSYNCMCLKOFHKRGDT/FSDM0VAFunctional Block DiagramSi3021Si3012Si3012 (SOIC or TSSOP)MCLKSCLKFSYNCSDISDOFC/RGTIsolationInterfaceIsolationInterfaceDCTerminationVREG2VREGDCTREXTIGNDRNG1RNG2 Off-HookQBQEDigitalInterface HybridOutInTXRXHYBDTSTATSTBIGNDC1BRNG1RNG2QBQE12345678161514131211109TXNCRXREXTDCTHYBDVREG2VREGRGDT/FSDOFHKMODERESETAOUTControlInterfaceRing DetectUS Patent # 5,870,046US Patent # 6,061,009Other Patents Pending

Si3035-DS12

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Si3035

2Rev. 1.2

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Si3035

TABLE OF CONTENTS

SectionPageElectrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Improved JATE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Pin Descriptions: Si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Rev. 1.23

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Si3035

Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter1

Ambient Temperature

Si3021 Supply Voltage, AnalogSi3021 Supply Voltage, Digital3Notes:

SymbolTAVA VD

Test Condition

K-Grade

Min204.753.0

Typ255.03.3/5.0

Max2705.255.25

Unit°CVV

1. The Si3035 specifications are guaranteed when the typical application circuit (including component tolerances) and any Si3021 and any Si3012 are used. See Figure16 on page 15 for typical application circuit.

2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.

3. The digital supply, VD, can operate from either 3.3V or 5.0V. The Si3021 supports interface to 3.3V logic when

operating from 3.3V. The 3.3V operation applies to both the serial port and the digital signalsRGDT, OFHK, RESET, M0, and M1.

Table 2. Loop Characteristics

(VA = Charge Pump, VD = +3.3 V ± 0.3V, TA = 0 to 70°C for K-Grade, Refer to Figure1)

Parameter

DC Termination VoltageDC Termination VoltageDC Ring Current (with caller ID)DC Ring Current (w/o caller ID)AC Termination ImpedanceOperating Loop CurrentLoop Current Sense BitsRing Voltage DetectRing Frequency

On-Hook Leakage Current

Ringer Equivalence Num. (with caller ID)Ringer Equivalence Num. (w/o caller ID)

SymbolVTRVTRIRDCIRDCZACTILPLCSVRDFRILKRENREN

Test ConditionIL = 20 mAIL = 105 mA

Min—12———20

Typ————600—15518——1.00.2

Max7.7—120—120—266811.67—

UnitVVmAµAΩmAmAVRMSHzµA——

LCS = Fh1801315

VBAT = –48V

———

TIP+600 ΩSi3012VTR10 µF–ILRINGFigure 1. Test Circuit for Loop Characteristics4

Rev. 1.2

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Si3035

Table 3. DC Characteristics, VD = +5V

(VA = +5 V ±5%, VD = +5V ±5%, TA = 0 to 70°C for K-Grade)

Parameter

High Level Input VoltageLow Level Input VoltageHigh Level Output VoltageLow Level Output VoltageInput Leakage CurrentPower Supply Current, AnalogPower Supply Current, Digital1Total Supply Current, Sleep Mode1Total Supply Current, Deep Sleep1,2

SymbolVIHVILVOHVOLILIAIDIA + IDIA + ID

Test ConditionMin3.5—

Typ—————0.3141.30.04

Max—0.8—0.4101182.50.5

UnitVVVVµAmAmAmAmA

IO = –2 mAIO = 2 mA

3.5—–10

VA pin VD pinPDN = 1, PDL = 0PDN = 1, PDL = 1

————

Notes:

1.All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded

(Static IOUT = 0mA).

2. RGDT is not functional in this state.Table 4. DC Characteristics, VD = +3.3V

(VA = Charge Pump, VD = +3.3V ± 0.3V, TA = 0 to 70°C for K-Grade)

Parameter

High Level Input VoltageLow Level Input VoltageHigh Level Output VoltageLow Level Output VoltageInput Leakage Current

Power Supply Current, Analog1,2Power Supply Current, Digital3Total Supply Current, Sleep Mode3Total Supply Current, Deep Sleep3,4Power Supply Voltage, Analog1,5

SymbolVIHVILVOHVOLILIAIDIA + IDIA + IDVA

Test ConditionMin2.0—

Typ—————0.391.20.044.6

Max—0.8— 0.35101122.50.55.00

UnitVVVVµAmAmAmA

IO = –2 mAIO = 2 mA

2.4—–10

VA pinVD pinPDN = 1, PDL = 0PDN = 1, PDL = 1Charge Pump On

————4.3

Notes:

1.Only a decoupling capacitor should be connected to VA when the charge pump is on.

2. There is no IA current consumption when the internal charge pump is enabled and only a decoupling cap is connected

to the VA pin.

3. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded

(Static IOUT = 0mA).

4. RGDT is not functional in this state.

5. The charge pump is recommended to be used only when VD < 4.5V. When the charge pump is not used, VA should be

applied to the device before VD is applied on power up if driven from separate supplies.

Rev. 1.25

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Si3035

Table 5. AC Characteristics

(VA = Charge Pump, VD = +3.3V ± 0.3V, TA = 0 to 70°C for K-Grade)

ParameterSample Rate1

PLL1 Output Clock FrequencyTransmit Frequency ResponseReceive Frequency ResponseTransmit Full Scale Level2 (0 dB gain)Receive Full Scale Level 2,3 (0 dB gain)Dynamic Range4Dynamic Range5

Total Harmonic Distortion6

Dynamic Range (call progress AOUT)THD (call progress AOUT)AOUT Full Scale LevelAOUT Output ImpedanceMute Level (call progress AOUT)Dynamic Range (caller ID mode)Caller ID Full Scale Level (0 dB gain)2

SymbolFsFPLL1

Test ConditionFs = FPLL2/5120FPLL1 = FMCLKM1/N1

Min7.236————

Typ——16160.980.988684–84—1.00.75 VD10—600.8

Max11.02558——————————————

UnitkHzMHzHzHzVPEAKVPEAKdBdBdBdB%VPPkΩdBdBVPEAK

Low –3 dB cornerLow –3 dB corner

VTXVRXDRDRTHDDRAOTHDAO

VIN = 1 kHz, –3 dBFSVIN = 1 kHz, –3 dBFSVIN = 1 kHz, –3 dBFS

VIN = 1 kHzVIN = 1 kHz

80——60———–90

DRCIDVCID

VIN = 1 kHz, –13dBFS——

Notes:

1.See Figure23 on page 22.

2. Parameter measured at TIP and RING of Figure16 on page 15.3. Receive Full Scale Level will produce – 0.9 dBFS at SDO.

4. DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth

is 300 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.

5. DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth

is 15 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.

6. THD = 20 log (RMS distortion/RMS signal). Applies to both the transmit and receive paths.

Sample Rate = 9.6kHz, Loop Current = 40 mA.

6Rev. 1.2

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Si3035

Table 6. Absolute Maximum Ratings

ParameterDC Supply Voltage

Input Current, Si3021 Digital Input PinsDigital Input Voltage

Operating Temperature RangeStorage Temperature Range

SymbolVD, VAIINVINDTATSTG

Value–0.5 to 6.0

±10

–0.3 to (VD + 0.3)

–40 to 100–65 to 150

UnitVmAV°C°C

Note:Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 7. Switching Characteristics—General Inputs

(VA = Charge Pump, VD = 3.0 to 5.25V, TA = 0 to 70°C for K-Grade, CL = 20 pF)

Parameter1Cycle Time, MCLKMCLK Duty CycleRise Time, MCLKFall Time, MCLKMCLK Before RESET ↑RESET Pulse Width2M0, M1 Before RESET↑3

Symboltmctdtytrtftmrtrltmxr

Min16.6740——10250150

Typ—50—————

Max10006055———

Unitns%nsnscyclesnsns

Notes:

1.All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

VIH = VD – 0.4V, VIL = 0.4V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.3. M0 and M1 are typically connected to VD or GND and should not be changed during normal operation.

trMCLKtmrtrlM0, M1tmxrtmctfVIHVILRESETFigure 2. General Inputs Timing Diagram

Rev. 1.27

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Si3035

Table 8. Switching Characteristics—Serial Interface (DCE = 0)

(VA = Charge Pump, VD = 3.0 to 5.25V, TA = 0 to 70°C for K-Grade, CL = 20 pF)

ParameterCycle time, SCLKSCLK duty cycle

Delay time, SCLK ↑ to FSYNC ↓Delay time, SCLK ↑ to SDO validDelay time, SCLK ↑ to FSYNC ↑Setup time, SDI before SCLK ↓Hold time, SDI after SCLK ↓Setup time, FC ↑ before SCLK ↑Hold time, FC ↑ after SCLK ↑

Symboltctdtytd1td2td3tsuthtsfcthfc

Min354————25204040

Typ1/256 Fs50———————

Max——102010————

Unitns%nsnsnsnsnsnsns

Note:All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4V, VIL = 0.4V

tcSCLKtd1td3VOHVOLFSYNC(mode 0)td3FSYNC(mode 1)td216 BitSDOD15tsuD14thD1D016 BitSDID15D14D1tsfcD0thfcFCFigure 3. Serial Interface Timing Diagram

8Rev. 1.2

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Si3035

Table 9. Switching Characteristics—Serial Interface (DCE = 1, FSD = 0)

(VA = Charge Pump, VD = 3.0 to 5.25V, TA = 0 to 70°C for K-Grade, CL = 20 pF)

Parameter1,2Cycle Time, SCLKSCLK Duty Cycle

Delay Time, SCLK ↑ to FSYNC ↑Delay Time, SCLK ↑ to FSYNC ↓Delay Time, SCLK ↑ to SDO validDelay Time, SCLK ↑ to SDO Hi-ZDelay Time, SCLK ↑ to RGDT ↓Delay Time, SCLK ↑ to RGDT ↑Setup Time, SDO Before SCLK ↓Hold Time, SDO After SCLK ↓Setup Time, SDI Before SCLKHold Time, SDI After SCLK

Symboltctdtytd1td2td3td4td5td6tsuthtsu2th2

Min354———0.25tc – 20

———25202520

Typ1/256 Fs50——————————

Max——10100.25tc + 20

202020————

Unitns%nsnsnsnsnsnsnsnsnsns

Notes:

1.All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4V, VIL = 0.4V.2. Refer to the section \"Multiple Device Support\" on page 25 for functional details.

32 SCLKstcSCLKtd1FSYNC(mode 1)td216 SCLKs16 SCLKstd2td5FSYNC(mode 0)td3SDO(master)tsuD15D14thD13D0td6td5td4td3SDO(slave 1)D15td5FSD(Mode 0)FSD(Mode 1)tsu2SDID15D14td2th2D13D0Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)Rev. 1.29

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Si3035

Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1)

(VA = Charge Pump, VD = 3.0 to 5.25V, TA = 0 to 70°C for K-Grade, CL = 20 pF)

Parameter1,2Cycle Time, SCLKSCLK Duty Cycle

Delay Time, SCLK ↑ to FSYNC ↑Delay Time, SCLK ↑ to FSYNC ↓Delay Time, SCLK ↑ to SDO validDelay Time, SCLK ↑ to SDO Hi-ZDelay Time, SCLK ↑ to RGDT ↓Setup Time, SDO Before SCLK ↓Hold Time, SDO After SCLK ↓Setup Time, SDI Before SCLKHold Time, SDI After SCLK

Symboltctdtytd1td2td3td4td5tsuthtsu2th2

Min354———0.25tc – 20

——25202520

Typ1/256 Fs50—————————

Max——10100.25tc + 20

2020————

Unitns%nsnsnsnsnsnsnsnsns

Notes:

1.All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4V, VIL = 0.4V.2. Refer to the section \"Multiple Device Support\" on page 25 for functional details.

tcSCLKtd1FSYNC(mode 1)td3SDO(master)D15tsuD14thD13D0td3SDO(slave 1)FSDtsu2SDID15D14td2td4D15td5th2D1D0Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)

10Rev. 1.2

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Si3035

Table 11. Digital FIR Filter Characteristics—Transmit and Receive

(VA = Charge Pump, VD = +5V ±5%, Sample Rate = 8kHz, TA = 0 to 70°C for K-Grade)

Parameter

Passband (0.1 dB)Passband (3 dB)

Passband Ripple Peak-to-PeakStopband

Stopband AttenuationGroup Delay

SymbolF(0.1 dB)F(3 dB)

Min00–0.1—–74

Typ———4.4—12/Fs

Max3.33.60.1———

UnitkHzkHzdBkHzdBsec

tgd

—

Note:Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9.

Table 12. Digital IIR Filter Characteristics—Transmit and Receive

(VA = Charge Pump, VD = +5V ±5%, Sample Rate = 8 kHz, TA = 0 to 70°C for K-Grade)

Parameter

Passband (3 dB)

Passband Ripple Peak-to-PeakStopband

Stopband AttenuationGroup Delay

SymbolF(3dB)

Min0–0.2—–40

Typ——4.4—1.6/Fs

Max3.60.2———

UnitkHzdBkHzdBsec

tgd

—

Note:Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 10, 11, 12, and 13. Figures 14 and 15 show

group delay versus input frequency.

Rev. 1.211

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Si3035

Attenuation—dBAttenuation—dBInput Frequency—HzInput Frequency—HzFigure 6. FIR Receive Filter ResponseFigure 8. FIR Transmit Filter Response

Attenuation—dBInput Frequency—HzAttenuation—dBInput Frequency—HzFigure 7. FIR Receive Filter Passband RippleFigure 9. FIR Transmit Filter Passband Ripple

For Figures 6–9, all filter plots apply to a sample rate of Fs = 8kHz. The filters scale with the sample rate as follows:

F(0.1 dB) = 0.4125 FsF(– 3 dB) = 0.45 Fs

where Fs is the sample frequency.

12Rev. 1.2

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Si3035

Attenuation—dBInput Frequency—HzAttenuation—dBInput Frequency—HzFigure 10. IIR Receive Filter ResponseFigure 12. IIR Transmit Filter Response

Attenuation—dBInput Frequency—HzAttenuation—dBInput Frequency—HzFigure 11. IIR Receive Filter Passband Ripple

Figure 13. IIR Transmit Filter Passband Ripple

For Figures 10–13, all filter plots apply to a sample rate of Fs = 8kHz. The filters scale with the sample rate as follows:

F(–3 dB) = 0.45 Fs

where Fs is the sample frequency.

Rev. 1.213

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Si3035

Delay—µsInput Frequency—HzDelay—µsInput Frequency—HzFigure 14. IIR Receive Group DelayFigure 15. IIR Transmit Group Delay

14Rev. 1.2

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Rev. 1.215DecouplingcapforU1VDVCCR3DecouplingcapforU1VANoGroundPlaneInDAASectionC1010D3R1C3Z4BAV99Q1R5RGDTbM0OFHKbU11FSYNCbMCLK2MCLKOFHK16U2SCLK3FSYNCRGDT154SCLK1Si301216R4R21M01413TSTA15SDO5VD14SDI6SDOGNDVA12R27R2823TSTBTXQ27SDIC1A114IGNDNC213+105C1BRX12RESETbFC8FCRESETAOUTM19RNG1REXTC167RNG211C5R188QBHYBDDCT10Si3021QEVREG2VREG9R6SOICPinoutAOUTC30C12C23+R2Z1D4C20M1BAV99Z5C2C6C16Q3R23C8R10FB2RINGD2C25C32C9C11RV1RV2D1C24C31R22C7R9TIPC4FB1Note1:R3isnotrequiredwhenVcc=3.3Vandthechargepumpisenabled(CPE=1).Note2:IfJATEsupportisnotrequired,R21,C12andC23mayberemoved(R21iseffectively0ohms)andR4shouldbechangedtoa604ohm,1/4W,+-1%.Note3:SeeAppendixforapplicationsrequiringUL19503rdEditioncompliance.Figure 16. Typical Application Schematic

Typical Application CircuitSi3035元器件交易网www.cecb2b.com

Si3035

Bill of Materials

Table 13. Component Values—Typical Application

Component1

C1,C4C2C3C5C6,C10,C16C7,C8,C9C11C122C232

C24, C25, C31,C323

C304D1,D25D3,D4FB1,FB2Q1,Q3Q2RV1RV2R1R2R36R42,R18,R212

R5,R6R9,R10R22,R23R27,R28U1U2Z1Z4,Z5

Value

150 pF, 3kV, X7R, ±20%

Not Installed0.22 µF, 16V, X7R, ±20%1 µF, 16V, Tant/Elec, ±20%0.1 µF, 16V, X7R, ±20%15 nF, 250 V, X7R, ±20%39 nF, 16V, X7R, ±20%2.7 nF, 16V, X7R, ±20%0.1 µF, 16V, Tant/Elec/X7R, ±20%

1000 pF, 3kV, X7R, ±10%

Not Installed

Dual Diode, 300 V, 225 mABAV99 Dual Diode, 70 V, 350 mW

Ferrite BeadA42, NPN, 300 VA92, NPN, 300 VSidactor, 275 V, 100 A

MOV, 240 V51 Ω, 1/2 W ±5%15 Ω, 1/4 W ±5%Not Installed301 Ω, 1/10 W, ±1%36 kΩ, 1/10 W ±5%2 kΩ, 1/10 W ±5%20 kΩ, 1/10 W ±5%10 Ω, 1/10 W ±5%

Si3021Si3012Zener diode, 18VZener diode, 5.6V, 1/2 W

Supplier(s)

Novacap, Venkel, Johanson, Murata,

Panasonic, SMEC

Novacap, Johanson, Murata, Panasonic, SMEC

Novacap, Venkel, Johanson, Murata, Panasonic, SMEC

Central Semiconductor

Diodes, Inc., OnSemiconductor, Fairchild

Murata

OnSemiconductor, FairchildOnSemiconductor, Fairchild

Teccor, ST Microelectronics, Microsemi, TI

Panasonic

Silicon LabsSilicon Labs

Vishay, Rohm, OnSemiconductorDiodes, Inc., OnSemiconductor, Fairchild

Notes:

1.The following reference designators were intentionally omitted: C13–C15, C17–C22, C26–C29, R7, R8, R11–R17,

R19, and R20.

2. If JATE support is not required, C12, and C23 may be removed.

3. Alternate population option is C24, C25 (2200pF, 3 kV, X7R, ±10% and C31, C32 not installed).4. Install only if needed for improved radiated emissions performance (10 pF, 16V, NPO, ±10%).5. Several diode bridge configurations are acceptable (suppliers include General Semi, Diodes Inc.)

6. If the charge pump is not enabled (with the CPE bit in Register6), VA must be 4.75 to 5.25 V. R3 can be installed with

a 10Ω, 1/10 W, ±5% if VD is also 4.75 to 5.25 V.

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Analog Output

Figure17 illustrates an optional application circuit to support the analog output capability of the Si3035 for callprogress monitoring purposes. The ARM bits in Register6 allow the receive path to be attenuated by 0dB, –6dB,or –12dB. The ATM bits, which are also in Register6, allow the transmit path to be attenuated by –20dB, –26dB,or –32dB. Both the transmit and receive paths can also be independently muted.

+5 VC2AOUTC1C6R1R3365C5+C4+2–4C3R2SpeakerFigure 17. Optional Connection to AOUT for a Call Progress Speaker

‘

Table 14. Component Values—Optional Connection to AOUT

SymbolC1C2, C3, C5

C4C6R1R2R3U1

Value

2200 pF, 16 V, ±20%0.1 µF, 16 V, ±20%100 µF, 16 V, Elec. ±20%820 pF, 16 V, ±20%3 kΩ, 1/10 W, ±5%10 Ω, 1/10 W, ±5%47 kΩ, 1/10 W, ±5%

LM386

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Si3035

Functional Description

The Si3035 is an integrated chipset that provides alow-cost, isolated, silicon-based interface to thetelephone line. The Si3035 saves cost and board areaby eliminating the need for a modem AFE or serialcodec. It also eliminates the need for an isolationtransformer, relays, opto-isolators, and a 2- to 4-wirehybrid. The Si3035 solution requires only a fewlow-cost, discrete components to achieve fullcompliance with FCC Part68 and JATE out-of-bandnoise requirements. See Figure16 on page 15 for atypical application circuit. See the pin-compatibleSi3034 or Si3044 data sheets for designs requiringglobal support.

The Si3035 North America/Japan DAA offers a numberof new features not supported by the Si3032 device.These include operation from a single 3.3V powersupply, JATE (Japan) filter option, finer resolution forboth transmit and receive levels on AOUT (call progressoutput), daisy-chaining for up to eight devices, and anoptional IIR filter. Table15 summarizes the new Si3035features.

procedure:

1.Program the PLLs with registers 7 to 9 (N1[7:0], M1[7:0],

N2[3:0] and M2[3:0]) to the appropriate divider ratios for the supplied MCLK frequency and desired sample rate, as defined in \"Clock Generation Subsystem\" on page 20.2.Wait until the PLLs are locked. This time is between

100µS and 1ms.3.Write an 0x80 into Register6. This enables the charge

pump for the VA pin, powers up the line-side chip (Si3012), and enables the AOUT for call progress monitoring.

After this procedure is complete, the Si3035 is ready forring detection and off-hook.

Isolation Barrier

The Si3035 achieves an isolation barrier through alow-cost, high-voltage capacitor in conjunction withSilicon Laboratories’ proprietary ISOcap signalprocessing techniques. These techniques eliminate anysignal degradation due to capacitor mismatches,common mode interference, or noise coupling. Asshown in Figure16 on page 15, the C1, C2, and C4capacitors isolate the Si3021 (DSP-side) from theSi3012 (line-side). All transmit, receive, control, andcaller ID data are communicated through this barrier.The ISOcap inter-chip communication is disabled bydefault. To enable it, the PDL bit in Register6 must becleared. No communication between the Si3021 andSi3012 can occur until this bit is cleared. The clockgenerator must be programmed to an acceptablesample rate prior to clearing the PDL bit.

Table 15. New Si3035 Features

CategoryDaisy-ChainingOptional IIR FilterReceive GainTransmit Attenuation

VAVD

JATE SupportAOUT Levels (dB)

Si3032——0, 6dB0, –3dB5V3.3V or 5V

—0, mute

Si3035Up to 8 Devices

Yes0, 3, 6, 9, 12dB0, –3, –6 –9,–12dB3.3V* or 5V3.3V or 5V

Yes0, –6, –12, mute

Off-Hook

The communication system generates an off-hookcommand by applying logic 0 to the OFHK pin or writinga logic 1 to bit 0 of control Register5. The OFHK pinmust be enabled by setting bit 1 (OHE) of Register5.With OFHK at logic 0, the system is in an off-hook state.This state is used to seize the line for incoming/outgoingcalls and can also be used for pulse dialing. With OFHKat logic 1, negligible DC current flows through thehookswitch. When a logic 0 is applied to the OFHK pin,the hookswitch transistor pair, Q1 and Q2, turn on. Thenet effect of the off-hook signal is the application of atermination impedance across TIP and RING and theflow of DC loop current. The termination impedance hasboth an AC and a DC component.

The AC termination impedance is a 604-Ω resistor,which is connected to the TX pin. The DC termination isa 51-Ω resistor, which is connected to the DCT pin.When executing an off-hook sequence, the Si3035requires 1548/Fs seconds to complete the off-hook andprovide phone line data on the serial link. This includesthe 12/Fs filter group delay. If necessary, for the shortest

*Note: The VA supply is internally generated by an on-chip

charge pump.

Initialization

When the Si3035 is initially powered up, the RESET pinshould be asserted. When the RESET pin isdeasserted, the registers will have default values. Thisreset condition guarantees the line-side chip (Si3012) ispowered down with no possibility of loading the line (i.e.,off-hook). The following is an example initialization

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delay, a higher Fs may be established prior to executing the off-hook, such as an Fs of 10.286 kHz. The delayallows line transients to settle prior to normal use.

Improved JATE Support

The HYBD pin connects to a node on the internal hybridcancellation circuit providing a pin for a balancingcapacitor, C12. C23 adds the necessary transmitout-of-band filtering required to meet JATE out-of-bandnoise specifications. The addition of C23 alters thetransmit path frequency response which must bebalanced with capacitor C12 to obtain maximum hybridcancellation.

Products using the Si3035 which have been submittedfor JATE approval should document a waiver for theJATE DC Termination specification. This specification ismet in the Si3034 global DAA device.

Ring Detect

The ring signal enters the Si3035 through low valuecapacitors connected to TIP and RING. RGDT is aclipped, half-wave rectified version of the ringingwaveform. See Figure18 for a timing diagram of theRGDT pin.

The integrated ring detect of the Si3035 allows thedevice to present the ring signal to the DSP, through theserial port, with no additional signaling required. Thesignal sent to the DSP is a clipped version of the originalring signal. In addition, the Si3035 passes through thecaller ID data unaltered.

The system can also detect an occurring ring by thestatus of the RDT bit of Register5. This bit is aread-only bit that is set when the line-side devicedetects a ring signal at RNG1 and RNG2. The RDT bitclears when the system either goes off-hook or 4.5 to 9seconds after the last ring is detected.

If caller ID is supported in the system, the designer canenable the Si3035 to pass this information to the SDOoutput. Following the completion of the first ring, thesystem should set the ONHM bit (Register5, bit3). Thisbit must be cleared at the conclusion of the receipt ofthe caller ID data and prior to the next ring burst.

The Si3021 can support a wake-up-on-ring functionusing the RGDT signal. Refer to \"Power Management\"on page 24 for more details.

Digital Interface

The Si3035 has two serial interface modes that supportmost standard modem DSPs. The M0 and M1 modepins select the interface mode. The key differencebetween these two serial modes is the operation of theFSYNC signal. Table16 summarizes the serial modedefinitions.

Table 16. Serial Modes

Mode M1 M00123

Description

0 0FSYNC frames data

0 1FSYNC pulse starts data frame 1 0Slave mode 1 1Reserved

First Ring0.2–3.0 secondsRNG1/RNG20.5–1.5 Sec.> 0.2 Sec.DATARGDTSDODIGITIZED LINE SIGNALFigure 18. Ring Detect Timing

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The digital interface consists of a single, synchronousserial link which communicates both telephony andcontrol data.

In Serial mode 0 or 1, the Si3021 operates as a master,where the master clock (MCLK) is an input, the serialdata clock (SCLK) is an output, and the frame syncsignal (FSYNC) is an output. The MCLK frequency andthe value of the sample rate control registers 7, 8, 9,and 10 determine the sample rate (Fs). The serial portclock, SCLK, runs at 256 bits per frame, where theframe rate is equivalent to the sample rate. Refer to\"Clock Generation Subsystem\" on page 20 for moredetails on programming sample rates.

The Si3035 transfers 16-bit or 15-bit telephony data inthe primary timeslot and 16-bit control data in thesecondary timeslot. Figure19 and Figure20 show therelative timing of the serial frames. Primary framesoccur at the frame rate and are always present. Tominimize overhead in the external DSP, secondaryframes are present only when requested.

Two methods exist for transferring control information inthe secondary frame. The default power-up mode usesthe LSB of the 16-bit transmit (TX) data word as a flagto request a secondary transfer. In this mode, only15-bit TX data is transferred, resulting in a loss of SNRbut allowing software control of the secondary frames.As an alternative method, the FC pin can serve as ahardware flag for requesting a secondary frame. Theexternal DSP can turn on the 16-bit TX mode by settingthe SB bit of Register1. In the 16-bit TX mode, thehardware FC pin must be used to request secondarytransfers.

Communications Frame 1 (CF1)Figure21 and Figure22 illustrate the secondary frameread cycle and write cycle, respectively. During a readcycle, the R/W bit is high and the 5-bit address fieldcontains the address of the register to be read. Thecontents of the 8-bit control register are placed on theSDO signal. During a write cycle, the R/W bit is low andthe 5-bit address field contains the address of theregister to be written. The 8-bit data to be writtenimmediately follows the address on SDI. Only oneregister can be read or written during each secondaryframe. See \"Control Registers\" on page 34 for theregister addresses and functions.

In serial mode 2, the Si3021 operates as a slave device,where the MCLK is an input, the SCLK is a no connect(except for the master device for which it is an output),and the FSYNC is an input. In addition, the RGDT/FSDpin operates as a delayed frame sync (FSD) and theFC/RGDT pin operates as ring detect (RGDT). In thismode, FC operation is not supported. For further detailson operating the Si3021 as a slave device, refer to\"Multiple Device Support\" on page 25.

Clock Generation Subsystem

The Si3035 contains an on-chip clock generator. Usinga single MCLK input frequency, the Si3035 cangenerate all the desired standard modem sample rates,as well as the common 11.025 kHz rate for audioplayback.

The clock generator consists of two PLLs (PLL1 andPLL2) that achieve the desired sample frequencies.Figure23 on page 22 illustrates the clock generator.

(CF2)PrimaryFSYNCPrimarySecondaryFC0D15 – D1 D0 = 1 (Software FC Bit)D15 – D1 D0 = 0 (Software FC Bit)XMT DataSDIXMT DataSecondaryDataSDORCV DataSecondaryDataRCV Data16 SCLKS128 SCLKS256 SCLKSFigure 19. Software FC Secondary Request20

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Communications Frame 1 (CF1)(CF2)PrimaryFSYNCPrimarySecondaryFC0D15–D0SDIXMT DataSecondaryDataXMT DataSDORCV DataSecondaryDataRCV Data16 SCLKS128 SCLKS256 SCLKSFigure 20. Hardware FC Secondary Request

FSYNC(mode 0)FSYNC(mode 1)D15 D14 D13 D12 D11 D10 D9 D8 D7D0SDI001AAAAAR/WD7 D6 D5 D4 D3 D2 D1 D0SDODDDDDDDDFigure 21. Secondary Communication Data Format—Read Cycle

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FSYNC(mode 0)FSYNC(mode 1)D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0SDI000AAAAADDDDDDDDR/WSDOFigure 22. Secondary Communication Data Format—Write Cycle

FUP1FPLL1DIV25FUP210FPLL2MCLKDIVN18bitsPLL1DIVM18bitsDIVN24bitsPLL2DIVM24bitsDIV51024·Fs01DIV16CGMBitFigure 23. Clock Generation Subsystem

The architecture of the dual PLL scheme allows for fastlock time on initial start-up, fast lock time whenchanging modem sample rates, high noise immunity,and the ability to change modem sample rates with asingle register write. A large number of MCLKfrequencies between 1MHz and 60MHz are supported.MCLK should be from a clean source, preferablydirectly from a crystal with a constant frequency and nodropped pulses.

In serial mode 2, the Si3021 operates as a slave device.The clock generator is configured (by default) to set theSCLK output equal to the MCLK input. The net effect isthe clock generator multiplies the MCLK input by 20. Forfurther details of slave mode operation, refer to \"MultipleDevice Support\" on page 25.

Programming the Clock Generator

As noted in Figure23, the clock generator must output aclock equal to 1024Fs, where Fs is the desiredsample rate. The 1024Fs clock is determined throughprogramming of the following registers:

\"\"

When using the Si3035 for modem applications, theclock generator can be programmed to allow for a singleregister write to change the modem sampling rate.These standard sample rates are shown in Table17.The programming method is described below.

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Table 17. N2, M2 Values (CGM = 0, 1)

Fs (Hz)72008000822984009000960010286

N22976437

M2210875410

Table 18. MCLK Examples

MCLK (MHz)

1.84324.00004.09605.06886.00006.14408.19209.216010.000010.368011.059212.28814.745616.000018.432024.576025.804833.868844.236846.080047.923248.000056.000060.0000

PLL Lock Times

The Si3035 changes sample rates very quickly.However, lock time will vary based on the programmingof the clock generator. The major factor contributing toPLL lock time is the CGM bit. When the CGM bit is used(set to 1), PLL2 will lock slower than when CGM is 0.The following relationships describe the boundaries onPLL locking time:

PLL1 lock time < 1 ms (CGM = 0,1)

PLL2 lock time: 100 us to 1ms (CGM = 0)PLL2 lock time <1 ms (CGM = 1)

N1151115132125931251327147965131253525

M1207298048622541443210351827510160125410963624

CGM010010101000010100100011

The main design consideration is the generation of abase frequency, defined as the following:

F⋅M1MCLK

FBase=----------------------------------=36.864MHz,CGM=0

N1⋅M1⋅16F

MCLK

FBase=---------------------------------------------=36.864MHz,CGM=1

N1⋅25

N1 (Register7) and M1 (Register8) are 8-bit unsignedvalues. FMCLK is the clock provided to the MCLK pin.Table18 lists several standard crystal oscillator ratesthat could be supplied to MCLK. This list simplyrepresents a sample of MCLK frequency choices. Manymore are possible.

After the first PLL has been setup, the second PLL canbe programmed easily. The values for N2 and M2(Register9) are shown in Table17. N2 and M2 are 4-bitunsigned values.

When programming the registers of the clock generator,the order of register writes is important. For PLL1updates, N1 (Register7) must always be written first,immediately followed by a write to M1 (Register8). ForPLL2, the CGM bit must be set as desired prior towriting N2/M2 (Register9). Changes to the CGM bitonly take effect when N2/M2 are written.

Note:The values shown in Table17 and Table18 satisfy the

equations above. However, when programming theregisters for N1, M1, N2, and M2, the value placed inthese registers must be one less than the value calcu-lated from the equations. For example, for CGM = 0with a MCLK of 48.0MHz, the values placed in the N1and M1 registers would be 0x7C and 0x5F, respec-tively. If CGM = 1, a non-zero value must be pro-grammed to Register9 in order for the 16/25 ratio totake effect.

For modem designs, it is recommended that PLL1 beprogrammed during initialization. No furtherprogramming of PLL1 is necessary. The CGM bit andPLL2 can be programmed for the desired initial sample

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rate, typically 7200Hz. All further sample rate changesare then made by simply writing to Register9 to updatePLL2.

The final design consideration for the clock generator isthe update rate of PLL1. The following criteria must besatisfied in order for the PLLs to remain stable:

FMCLK

F=---------------------≥144kHzUP1N1

PDN bit is cleared. The Si3021 is fully operational,

except for the ISOcap link. No communication betweenthe Si3021 and Si3012 can occur during resetoperation. Any bits associated with the Si3012 are notvalid in this mode.

The most common mode of operation is the normaloperation. In this mode, the PDL and PDN bits arecleared. The Si3021 is fully operational and the ISOcaplink is passing information between the Si3021 and theSi3012. The clock generator must be programmed to avalid sample rate prior to entering this mode.

The Si3035 supports a low-power sleep mode. Thismode supports the popular wake-up-on-ring feature ofmany modems. The clock generator registers 7, 8, and9 must be programmed with valid non-zero values priorto enabling sleep mode. Then, the PDN bit must be setand the PDL bit cleared. When the Si3035 is in sleepmode, the MCLK signal may be stopped or remainactive, but it must be active before waking up theSi3035. The Si3021 is non-functional except for theISOcap and RGDT signal. To take the Si3035 out ofsleep mode, pulse the reset pin (RESET) low.

In summary, the power down/up sequence for sleepmode is as follows:

1.Registers 7, 8, and 9 must have valid non-zero values.2.Set the PDN bit (Register6, bit3) and clear the PDL bit

(Register6, bit 4).3.MCLK may stay active or stop.

4.Restore MCLK before initiating the power-up sequence.5.Reset the Si3035 using RESET pin (after MCLK is present).6.Program registers to desired settings.

Where FUP1 is shown in Figure23 on page 22.Setting Generic Sample Rates

The above clock generation description focuses on thecommon modem sample rates. An application mayrequire a sample rate not listed in Table17, such as thecommon audio rate of 11.025 kHz. The restrictions andequations above still apply; however, a more genericrelationship between MCLK and Fs (the desired samplerate) is needed. The following equation describes thisrelationship:

5⋅1024⋅FsM1⋅M2----------------------=ratio⋅-------------------------------MCLKN1⋅N2

where Fs is the sample frequency, ratio is 1 for

CGM=0 and 25/16 for CGM=1, and all other symbolsare shown in Figure23 on page 22.

By knowing the MCLK frequency and desired samplerate, the values for the M1, N1, M2, N2 registers can bedetermined. When determining these values, rememberto consider the range for each register as well as theminimum update rate for the first PLL.

The values determined for M1, N1, M2, and N2 must beadjusted by minus one when determining the valuewritten to the respective registers. This is due to internallogic, which adds one to the value stored in the register.This addition allows the user to write a zero value in anyof the registers and the effective divide by is one. Aspecial case occurs when both M1 and N1 and/or M2and N2 are programmed with a zero value. When Mxand Nx are both zero, the corresponding PLLx isbypassed. Note that if M2 and N2 are set to zero, theratio of 25/16 is eliminated and cannot be used in theabove equation. In this condition the CGM bit has noeffect.

The Si3035 also supports an additional power-downmode. When both the PDN (Register6, bit3) and PDL(Register6, bit4) are set, the chipset enters a completepower-down mode and draws negligible current (deepsleep mode). PLL2 should be turned off prior to enteringdeep sleep mode (i.e., set Register9 to 0 and thenRegister6 to 0x18). In this mode, the RGDT pin doesnot function. Normal operation may be restored usingthe same process for taking the chipset out of sleepmode.

Power Management

The Si3035 supports four basic power managementoperation modes: normal operation, reset operation,sleep, and full power down. The power managementmodes are controlled by the PDN and PDL bits ofRegister6.

On power up, or following a reset, the Si3035 is in resetoperation. In this mode, the PDL bit is set, while the

Analog Output

The Si3035 supports an analog output (AOUT) fordriving the call progress speaker found with most oftoday’s modems. AOUT is an analog signal that iscomprised of a mix of the transmit and receive signals.The receive portion of this mixed signal has a 0dB gain,while the transmit signal has a gain of –20dB.

The AOUT level can be adjusted via the ATM and ARMbits in control Register6. The transmit portion of the

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Si3035

AOUT signal can be set to –20dB, –26dB, –32dB, ormute. The receive portion of the AOUT signal can beset to 0dB, –6dB, –12dB, or mute. Figure17 on page17 illustrates a recommended application circuit. In theconfiguration shown, the LM386 provides a gain of26dB. Additional gain adjustments may be made byvarying the voltage divider created by R1 and R3 ofFigure17.

An LCS value of zero means the loop current is lessthan required for normal operation and the systemshould be on-hook. Typically, an LCS value of 15 meansthe loop current is greater than 155mA.

The LCS detector has a built-in hysteresis of 2mA ofcurrent. This allows for a stable LCS value when theloop current is near a transition level. The LCS value isa rough approximation of the loop current, and thedesigner is advised to use this value in a relative meansrather than an absolute value.

This feature enables the host processor to detect if anadditional line has “picked up” while the modem istransferring information. In the case of a second phonegoing off-hook, the loop current falls approximately 50%and is reflected in the value of the LCS bits.

On-Hook Line Monitor

The Si3035 allows the user to detect line activity whenthe device is in an on-hook state. When the system ison-hook, the line data can be passed to the DSP acrossthe serial port while drawing a small amount of DCcurrent from the line. This feature is similar to thepassing of line information (such as caller ID), whileon-hook, following a ring signal detection. To activatethis feature, set the ONHM bit in Register5.

The on-hook line monitor can also be used to detectwhether a phone line is physically connected to theSi3012 and associated circuitry. When the on-hook linemonitor is activated (if no line is connected), the outputof SDO will move towards a negative full scale value (–32768). The value is guaranteed to be at least 89% ofnegative full scale.

If a line is present while in on-hook line monitor mode,SDO will have a near zero value. The designer mustallow for the group delay of the receive filter (12/Fs)before making a decision.

Multiple Device Support

The Si3035 supports the operation of up to sevenadditional devices on a single serial interface. Figure25on page 27 shows the typical connection of the Si3035and one additional serial voice codec (Si3000).

The Si3035 must be the master in this configuration. Thesecondary codec should be configured as a slave devicewith SCLK and FSYNC as inputs. On power up, theSi3035 master will be unaware of the additional codecon the serial bus. The FC/RGDT pin is an input,operating as the hardware control for secondary frames.The RGDT/FSD pin is an output, operating as the activelow ring detection signal. It is recommended that themaster device be programmed for master/slave modeprior to enabling the ISOcap, because a ring signalwould cause a false transition to the slave device’sFSYNC.

Register14 provides the necessary control bits toconfigure the Si3035 for master/slave operation. Bit 0(DCE) sets the Si3035 in master/slave mode, alsoreferred to as daisy-chain mode. When the DCE bit isset, the FC/RGDT pin becomes the ring detect outputand the RGDT/FSD pin becomes the frame sync delayoutput.

Bits 7:5 (NSLV2:NSLV0) set the number of slaves to besupported on the serial bus. For each slave, the Si3035will generate a FSYNC to the DSP. In daisy-chain mode,the polarity of the ring signal can be controlled by bit 1(RPOL). When RPOL=1, the ring detect signal (nowoutput on the FC/RGDT pin) is active high.

The Si3035 supports a variety of codecs (e.g., Si3000)as well as additional Si3035s. The type of slave codec(s)used is set by bits 4:3 (SSEL1:SSEL0). These bitsdetermine the type of signalling used in the LSB of SDO.This assists the DSP in isolating which data stream isthe master and which is the slave. If the LSB is used for

Loop Current Monitor

When the system is in an off-hook state, the LCS bits ofRegister12 indicate the approximate amount of DCloop current that is flowing in the loop. The LCS is a4-bit value ranging from zero to fifteen. Each unitrepresents approximately 6mA of loop current fromLCS codes 1–14. The typical LCS transfer function isshown in Figure24.

1510LCSBIT5006121824303642485460667278849096Loop Current (mA)155Figure 24. Typical LCS Transfer Function

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signalling, the master device will have a unique settingrelative to the slave devices. The DSP can use thisinformation to determine which FSYNC marks thebeginning of a sequence of data transfers.

The delayed frame sync (FSD) of each device issupplied as the FSYNC of each subsequent slavedevice in the daisy chain. The master Si3035 willgenerate an FSYNC signal for each device every 16 or32 SCLK periods. The delay period is set by Register14,bit 2 (FSD). Figures 26–29 show the relative timing fordaisy chaining operation. Primary communicationframes occur in sequence, followed by secondarycommunication frames, if requested. Whenwriting/reading the master device via a secondary frame,all secondary frames of the slave devices must bewritten as well. When writing/reading a slave device viaa secondary frame, the secondary frames of the masterand all other slaves must be written as well. \"Nooperation\" writes/reads to secondary frames areaccomplished by writing/reading a zero value to addresszero.

If FSD is set for 16 SCLK periods between FSYNCs,only serial mode 1 can be used. In addition, the slavedevices must delay the tri-state to active transition oftheir SDO sufficiently from the rising edge of SCLK toavoid bus contention.

The Si3035 supports the operation of up to eight Si3035devices on a single serial bus. The master Si3035 mustbe configured in serial mode 1. The slave(s) Si3035 isconfigured in serial mode 2. Figure30 shows a typicalmaster/slave connection using three Si3035 devices.When in serial mode 2, FSYNC becomes an input,RGDT/FSD becomes the delay frame sync output, andFC/RGDT becomes the ring detection output. Inaddition, the internal PLLs are fixed to a multiply by 20.This provides the desired sample rate when the master’sSCLK is provided to the slave’s MCLK. The SCLK of theslave is a no connect in this configuration. The delaybetween FSYNC input and delayed frame sync output(RGDT/FSD) will be 16 SCLK periods. The RGDT/FSDoutput has a waveform identical to the FSYNC signal inserial mode 0. In addition, the LSB of SDO is set to zeroby default for all devices in serial mode 2.

Register13 must be 0.

The receive path can support gains of 0, 3, 6, 9, and12dB. The gain is selected by bits 2:0 (ARX2:ARX0).The receive path can also be muted by setting bit 3(RXM). The transmit path can support attenuations of 0,3, 6, 9, and 12dB. The attenuation is selected by bits6:4 (ATX2:ATX0). The transmit path can also be mutedby setting bit 7 (TXM).

Filter Selection

The Si3035 supports additional filter selections for thereceive and transmit signals. When set, the IIRE bit ofRegister16 enables the IIR filters defined in Table12 onpage11. This filter provides a much lower, howevernon-linear, group delay than the default FIR filters.

Gain Control

The Si3035 supports multiple gain and attenuationsettings for the receive and transmit paths, respectively,via Register13. When the ARX bit is set, 6dB of gain isapplied to the receive path. When the ATX bit is set,–3dB of gain is applied to the transmit path.

Register15 can be used to provide additional gaincontrol. For Register15 to have an effect on the receiveand transmit paths, the ATX and ARX bits of

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MCLKDSPSCLKSDOSDIFSYNCSi3021MCLKSCLKSDISDOFSYNCINT0FC/RGDTRGDT/FSDM0M1VCC47 kΩ47 kΩ+5 V47 kΩSi3000SCLKMCLKFSYNCSDISDOVoiceCodecFigure 25. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem)

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Si3035

MasterSlave 1Serial Mode 1Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1Serial Mode 2Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1Primary Frame (Data)Secondary Frame (Control)128 SCLKs128 SCLKsMaster FSYNC32 SCLKsMaster FSD/Slave1 FSYNC32 SCLKsSDI [0]SDI [15..1]SDO [0]SDO[15..1]1Master1Master1Slave10Slave1MasterMasterMasterMasterSlave1Slave1Slave1Slave1CommentsPrimary frames with secondary frame requested via SDI[0] = 1Figure 26. Daisy Chaining of a Single Slave (Pulse FSD)

MasterSlave 1Serial Mode 1Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1Serial Mode 2Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1Primary Frame (Data)Secondary Frame (Control)128 SCLKs128 SCLKsMaster FSYNCMaster FSD/Slave1 FSYNC16 SCLKs16 SCLKs16 SCLKs16 SCLKsSDI [0]SDI [15..1]SDO [0]SDO[15..1]1Master1Master1Slave10Slave1MasterMasterMasterMasterSlave1Slave1Slave1Slave1CommentsPrimary frames with secondary frame requested via SDI[0] = 1Figure 27. Daisy Chaining of a Single Slave (Frame FSD)

28Rev. 1.2

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Rev. 1.229MasterSerial Mode 1Reg 14: NSLV = 7, SSEL = 2, FSD = 1, DCE = 1Slave 1Serial Mode 2Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1Primary Frame (Data)Secondary Frame (Control)128 SCLKs128 SCLKsMasterFSYNC16 SCLKsMaster FSD/Slave1 FSYNCSlave1 FSD/Slave2 FSYNCSlave2 FSD/Slave3 FSYNCSlave3 FSD/Slave4 FSYNCSlave4 FSD/Slave5 FSYNCSlave5 FSD/Slave6 FSYNCSlave6 FSD/Slave7 FSYNCSDI [0]11111111MasterSlave1Slave2Slave3Slave4Slave5Slave6Slave7SDI [15..1]MasterSlave1Slave2Slave3Slave4Slave5Slave6Slave7MasterSlave1Slave2Slave3Slave4Slave5Slave6Slave7SDO [0]10000000MasterSlave1Slave2Slave3Slave4Slave5Slave6Slave7SDO[15..1]MasterSlave1Slave2Slave3Slave4Slave5Slave6Slave7MasterSlave1Slave2Slave3Slave4Slave5Slave6Slave7CommentsPrimary frames with secondary frame requested via SDI[0] = 1Figure 28. Daisy Chaining of Eight DAAs

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Si3035

MasterSlave 1Serial Mode 0Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1Serial Mode 2Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1Primary Frame (Data)Secondary Frame (Control)128 SCLKs128 SCLKs16 SCLKsMaster FSYNCMaster FSD/Slave1 FSYNCSDI [0]SDI [15..1]SDO [0]SDO [15..1]Comments1Master1Master1Slave10Slave1MasterMasterMasterMasterSlave1Slave1Slave1Slave1Primary frames with secondary frame requested via SDI[0] = 1Figure 29. Daisy Chaining with Framed FSYNC and Framed FSD

30Rev. 1.2

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Si3035

MCLKDSPSCLKSDOSDIFSYNCSi3021–MasterMCLKSCLKSDISDOFSYNCINT0VCCFC/RGDTRGDT/FSDM1M047 kΩ47 kΩSi3021–Slave 1MCLKSCLKFSYNCSDISDORGDT/FSDVCCM1M0Si3021–Slave 2MCLKSCLKFSYNCSDISDORGDT/FSDVCCM1M0Figure 30. Typical Connection for Multiple Si3035s

Rev. 1.231

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Si3035

Revision Identification

The Si3035 provides the system designer the ability todetermine the revision of the Si3021 and/or the Si3012.Register 11 identifies the revision of the Si3021 with 4bits named REVA. Register 13 identifies the revision ofthe Si3012 with 4 bits named REVB. Table19 showsthe values for the various revisions.

can be used, the test circuit in Figure1 on page 4 isadequate. In addition, an off-hook sequence must beperformed to connect the power source to the line-sidechip.

For the start-up test mode, no line-side power isnecessary and no off-hook sequence is required. Thestart-up test mode is enabled by default. When the PDLbit (Register6, bit4) is set (the default case), the lineside is in a power-down mode and the DSP-side is in adigital loop-back mode. In this mode, data received onSDI is passed through the internal filters andtransmitted on SDO. This path will introduceapproximately 0.9dB of attenuation on the SDI signalreceived. The group delay of both transmit and receivefilters will exist between SDI and SDO. Clearing thePDL bit disables this mode and the SDO data isswitched to the receive data from the line side. Whenthe PDL bit is cleared the FDT bit (Register12, bit6) willbecome active, indicating the successfulcommunication between the line-side and DSP-side.This can be used to verify that the ISOcap link isoperational.

The remaining test modes require an off-hook sequenceto operate. The following sequence defines the off-hookrequirement:

1.Power up or reset.

2.Program clock generator to desired sample rate.3.Enable line-side by clearing PDL bit.4.Issue off-hook

5.Delay 1548/Fs to allow calibration to occur. 6.Set desired test mode.

Table 19. Revision Values

Revision

ABCDEG

Si3021100010011010———

Si3012———010001010111

Calibration

The Si3035 initiates an auto-calibration by defaultwhenever the device goes off-hook or experiences aloss in line power. Calibration is used to remove anyoffsets that may be present in the on-chip A/D converterwhich could affect the A/D dynamic range.Auto-calibration is typically initiated after the DAA DCtermination stabilizes and takes 512/Fs seconds tocomplete. Due to the large variation in line conditionsand line card behavior that may be presented to theDAA, it can be beneficial to use manual calibration inlieu of auto-calibration. Manual calibration should beexecuted as close as possible to 512/Fs seconds beforevalid transmit/receive data is expected.

The following steps should be taken to implementmanual calibration:

1.The CALD (auto-calibration disable—Register17) bit must

be set to 1. 2.The MCAL (manual calibration) bit must be toggled to 1

and then 0 to begin and complete the calibration. 3.The calibration will be completed in 512/Fs seconds.

The ISOcap digital loopback mode allows the datapump to provide a digital input test pattern on SDI andreceive that digital test pattern back on SDO. To enablethis mode, set the DL bit of Register1. In this mode, theisolation barrier is actually being tested. The digitalstream is delivered across the isolation capacitor, C1 ofFigure16 on page 15, to the line-side device andreturned across the same barrier. In this mode, the0.9dB attenuation and filter group delays also exist.The analog loopback mode allows an external device todrive the RX pin of the line-side chip and receive thesignal from the TX pin. This mode allows testing ofexternal components connecting the RJ-11 jack (TIPand RING) to the line side of the Si3035. To enable thismode, set the AL bit of Register2.

The final testing mode, internal analog loopback, allowsthe system to test the basic operation of thetransmit/receive path of the line side and the externalcomponents R4, R18, R21, and C5 of Figure16 onpage 15. In this test mode, the data pump provides a

In-Circuit Testing

The Si3035’s advanced design provides the modemmanufacturer with an increased ability to determinesystem functionality during production line tests, as wellas support for end-user diagnostics. Four loopbackmodes exist allowing increased coverage of systemcomponents. For three of the test modes, a line-sidepower source is needed. While a standard phone line

Rev. 1.2

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Si3035

digital test waveform on SDI. This data is passed acrossthe isolation barrier, looped from the TX to the RX pin,passed back across the isolation barrier, and presentedto the data pump on SDO. To enable this mode, clearthe HBE bit of Register2.

Clearing the HBE bit will cause a DC offset whichaffects the signal swing of the transmit signal. In this testmode, it is recommended that the transmit signal be12dB lower than normal transmit levels. This lowerlevel will eliminate clipping caused by the DC offsetwhich results from disabling the hybrid. It is assumed inthis test that the line AC impedance is nominally 600Ω.

Note:All test modes are mutually exclusive. If more than one

test mode is enabled concurrently, the results areunpredictable.

chip must be reset. This is accomplished by setting thePDL bit for at least 1ms.

Another useful bit is the communication link error (CLE)bit (Register12, bit7). The CLE bit indicates a time-outerror for the ISOcap link following a change to eitherPLL1 or PLL2. For more information, see “ClockGeneration Subsystem” on page20. When the CLE bitis set, the DSP-side chip has failed to receiveverification from the line side that the clock change hasbeen accepted in an expected period of time (less than10ms). This condition indicates a severe error inprogramming the clock generator or possibly a defectiveline-side chip.

Exception Handling

The Si3035 provides several mechanisms to determineif an error occurs during operation. Through thesecondary frames of the serial link, the controlling DSPcan read several status bits. The bit of highestimportance is the frame detect bit (FDT, Register12,bit6). This bit indicates that the DSP-side (Si3021) andline-side (Si3012) devices are communicating. Duringnormal operation, the FDT bit can be checked beforereading any bits that indicate information about the lineside. If FDT is not set, the following bits related to theline-side are invalid: RDT, LCS, CBID, and REVB. TheRGDT operation will also be non-functional.

Following power-up and reset, the FDT bit is not setbecause the PDL bit (Register6, bit4) defaults to 1. Inthis state, the ISOcap link is not operating and noinformation about the line-side can be determined. Theuser must program the clock generator to a validconfiguration for the system and clear the PDL bit toactivate the ISOcap link. While the Si3021 and Si3012are establishing communication, the Si3035 will notgenerate FSYNC signals. Establishing communicationwill take less than 10ms. Therefore, if the controllingDSP serial interface is interrupt driven, based on theFSYNC signal, the controlling DSP does not require aspecial delay loop to wait for this event to complete.The FDT bit can also indicate if the line-side executesan off-hook request successfully. If the line-side is notconnected to a phone line (i.e., the user fails to connecta phone line to the modem), the FDT bit remainscleared. The controlling DSP must allow sufficient timefor the line-side to execute the off-hook request. Themaximum time for FDT to be valid following an off-hookrequest is 10 ms. At this time, the LCS bits indicate theamount of loop current flowing. For more information,see “Loop Current Monitor” on page25. If the FDT bitfails to be set following an off-hook request, the line-side

Rev. 1.2

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Si3035

Control Registers

Any register not listed here is reserved and should not be written.

Table 20. Register Summary

RegisterName

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Control 1Control 2

DLHBE

SBRXE

3Control 3 4Control 4567891011121314151617

DAA Control 1DAA Control 2PLL1 Divide N1PLL1 Multiply

PLL2 Div./Mult. N2/M2PLL ControlChip RevisionLine Side StatusTransmit and Receive GainDaisy-Chain ControlTX/RX Gain Control

IIRFilterControlCalibration

NSLV2TXM00CLE

FDTCBIDNSLV1ATX20MCAL

NSLV0ATX10CALD

REVB[3:0]SSEL1ATX0IIRE

SSEL0RXM1

FSDARX20

REVA[3:0]LCS[3:0]

ARXRPOLARX10

ATXDCEARX00

N2[3:0]

CPE

ATM1

ARM1

OPOLPDL

ONHMPDN

RDT

OHEATM0

OHARM0

N1[7:0]M1[7:0]

M2[3:0]

CGM

34Rev. 1.2

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Si3035

D7SRR/W

D1DLR/W

D0SBR/W

Reset settings = 0000_0000Bit7

NameSR

Software Reset.

0 = Enables chip for normal operation.1 = Sets all registers to their reset value.Read returns zero.

Isolation Digital Loopback.

0 = Disables digital loopback mode across the isolation barrier.1 = Enables digital loopback mode across the isolation barrier.

Serial Digital Interface Mode.

0 = Operation is in 15-bit mode and the LSB of the data field indicates whether a secondary frame is required.

1 = The serial port is operating in 16-bit mode and requires use of the secondary frame sync signal, FC/RGDT, to initiate control data reads/writes.

Function

6:21

Reserved

0SB

Reset settings = 0000_0011Bit7:43

NameReserved

Read returns zero.

Analog Loopback.

0 = Disables analog loopback mode.1 = Enables analog loopback mode.Read returns zero.

Hybrid Enable.

0 = Disconnects hybrid in transmit path.1 = Connects hybrid in transmit path.Receive Enable.

0 = Disables receive path.1 = Enables receive path.

Function

D3ALR/W

D1HBER/W

D0RXER/W

ReservedHBE

0RXE

Rev. 1.235

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Si3035

Reset settings = 0000_0000Bit7:0

NameReserved

Read returns zero.

Function

Reset settings = 0000_0000Bit7:0

NameReserved

Read returns zero.

Function

36Rev. 1.2

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Si3035

Reset settings = 0000_0000Bit7:54

NameReservedOPOL

Read returns zero.

Off-Hook Polarity.

0 = Off-hook pin is active low.1 = Off-hook pin is active high.

On-Hook Line Monitor. 0 = Normal on-hook mode.

1 = Enables low-power monitoring mode allowing the DSP to receive line activity without going off-hook. This mode is used for caller ID detection.

Ring Detect.

0 = No ring is occurring. Reset either 4.5–9 seconds after last positive ring is detected or when the system executes an off-hook.1 = Indicates a ring is occurring.

Off-Hook Pin Enable.

0 = Off-hook pin is ignored.

1 = Enables the operation of the off-hook pin.

Off-Hook.

0 = Line side chip is on-hook.

1 = Causes the line side chip to go off-hook. This bit operates independently of OHE and is a logic OR with the off-hook pin when OHE = 1.

Function

D4OPOLR/W

D3ONHMR/W

D2RDTR

D1OHER/W

D0OHR/W

3ONHM

2RDT

1OHE

0OH

Rev. 1.237

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Si3035

D7CPER/W

ATM1ARM1R/W

R/W

PDL PDNR/W

R/W

ATM0ARM0R/W

R/W

Reset settings = 0111_0000Bit7

NameCPE

Function

Charge Pump Enable.

0 = Charge pump is disabled.

1 = Charge pump is enabled. (The VA pin should not be connected to a supply. VD = 3.3V ± 10%.)

AOUT Transmit Path Level Control.

00 = –20 dB transmit path attenuation for call progress AOUT pin only.01 = –32 dB transmit path attenuation for call progress AOUT pin only.10 = Mutes transmit path for call progress AOUT pin only.

11 = –26 dB transmit path attenuation for call progress AOUT pin only.

6,1ATM[1:0]

5,0

ARM[1:0]AOUT Receive Path Level Control.

00 = 0 dB receive path attenuation for call progress AOUT pin only.01 = –12 dB receive path attenuation for call progress AOUT pin only.10 = Mutes receive path for call progress AOUT pin only.

11 = –6 dB receive path attenuation for call progress AOUT pin only.PDL

Power Down Line-Side Chip.

0 = Normal operation. Program the clock generator before clearing this bit.1 = Places the Si3012 in power down or reset state.

Power Down.

0 = Normal operation.

1 = Powers down the Si3021. A pulse on RESET is required to restore normal operation.

3PDN

2ReservedRead returns zero.

N1[7:0]R/W

Reset settings = 0000_0000 (serial mode 0, 1, 2)Bit7:0

NameN1[7:0]

Function

N1 Divider.

Contains the (value – 1) for determining the output frequency on PLL1.

38Rev. 1.2

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Si3035

M1[7:0]R/W

Reset settings = 0000_0000 (serial mode 0, 1)Reset settings = 0001_0011 (serial mode 2)Bit7:0

NameM1[7:0]

Function

M1 Multiplier.

Contains the (value – 1) for determining the output frequency on PLL1

N2[3:0]R/W

M2[3:0]R/W

Reset settings = 0000_0000 (serial mode 0, 1, 2)Bit7:43:0

NameN2[3:0]M2[3:0]

Function

N2 Divider.

Contains the (value – 1) for determining the output frequency on PLL2.M2 Multiplier.

Contains the (value – 1) for determining the output frequency on PLL2.

Reset settings = 0000_0000Bit7:10

NameReservedCGM

Read returns zero.

Clock Generation Mode.

0 = No additional ratio is applied to the PLL and faster lock times are possible.

1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of MCLK frequencies while slowing down the PLL lock time.

Function

D0CGMR/W

Rev. 1.239

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Si3035

Reset settings = N/A

Bit7:43:0

NameReservedREVA[3:0]

Read returns zero.

Chip Revision.

Four-bit value indicating the revision of the Si3021 (DSP-side) chip.

Function

REVAR[3:0]

D7CLER/W

D6FDTR

LCS[3:0]

Reset settings = N/ABit7

NameCLE

Function

Communications (ISOcap Link) Error.

0 = ISOcap communication link between the Si3021 and the Si3012 is operating correctly.1 = Indicates a communication problem between the Si3021 and the Si3012. A write of 0 or a reset is required to clear this bit.

Frame Detect.

0 = Indicates ISOcap link has not established frame lock.1 = Indicates ISOcap link frame lock has been established.Read returns zero.

Loop Current Sense.

Four-bit value returning the loop current in 6mA increments. 0 = Loop current < 0.4 mA typical. 1111 = Loop current > 155 mA typical.See “Loop Current Monitor” on page25.

6FDT

5:43:0

ReservedLCS[3:0]

40Rev. 1.2

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Si3035

D6CBIDR

D1ARXR/W

D0ATXR/W

REVB[3:0]

Reset settings = 0000_0000Bit76

NameReservedCBID

Read returns zero.

Chip B ID.

0 = Indicates the line side is domestic only.

1 = Indicates the line side has international support.

Function

5:21

REVB[3:0]Chip Revision.

Four-bit value indicating the revision of the Si3012 (line-side) chip.ARX

Receive Gain.

0 = 0 dB gain is applied to the receive path.1 = 6 dB gain is applied to the receive path.

Note:This bit should be zero if using Register15 to control gain.

0ATX

Transmit Gain.

0 = 0 dB gain is applied to the receive path.

1 = –3 dB gain (attenuation) is applied to the transmit path.

Note:This bit should be 0 if using Register15 to control gain.

Rev. 1.241

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Si3035

D2FSDR/W

NSLV2NSLV1NSLV0SSEL1SSEL0R/W

R/W

RPOLDCER/W

R/W

Reset settings = 0000_0010 (serial mode 0, 1)Reset settings = 0011_1111 (serial mode 2)Bit7:5

Name

Function

NSLV[2:0]Number of Slave Devices.

000 = 0 slaves. Simply redefines the FC/RGDT and RGDT/FSD pins.001 = 1 slave device.010 = 2 slave devices.011 = 3 slave devices.

100 = 4 slave devices. (For four or more slave devices, the FSD bit MUST be set.)101 = 5 slave devices.110 = 6 slave devices.111 = 7 slave devices.SSEL[1:0]Slave Device Select.

00 = 16-bit SDO receive data.01 = Reserved.

10 = 15-bit SDO receive data. LSB = 1 for the Si3035 device.11 = 15-bit SDO receive data. LSB = 0 for the Si3035 device.FSD

Delayed Frame Sync Control.

0 = Sets the number of SCLK periods between frame syncs to 32.

1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when Si3035 devices are slaves. For the master Si3035, only serial mode 1 is allowed in this case. Ring Detect Polarity.

0 = The FC/RGDT pin (operating as ring detect) is active low.1 = The FC/RGDT pin (operating as ring detect) is active high.

Daisy-Chain Enable.

0 = Daisy chaining disabled.

1 = Enables the Si3035 to operate with slave devices on the same serial bus. The FC/RGDT signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the delayed frame sync signal. Note that ALL other bits in this register are ignored if DCE = 0.

4:3

1RPOL

0DCE

42Rev. 1.2

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Si3035

D7TXMR/W

D6ATX2R/W

D5ATX1R/W

D4ATX0R/W

D3RXMR/W

D2ARX2R/W

D1ARX1R/W

D0ARX0R/W

Reset settings = 0000_0000Bit7

NameTXM

Transmit Mute.

0 = Transmit signal is not muted.1 = Mutes the transmit signal.Analog Transmit Attenuation.000 = 0 dB attenuation.001 = 3 dB attenuation.010 = 6 dB attenuation.011 = 9 dB attenuation.1xx = 12 dB attenuation.

Note:Register 13 ATX bit must be 0 if these bits are used.

Function

6:4ATX[2:0]

3RXM

Receive Mute.

0 = Receive signal is not muted.1 = Mutes the receive signal.Analog Receive Gain.000 = 0 dB gain.001 = 3 dB gain.010 = 6 dB gain.011 = 9 dB gain1xx = 12 dB gain.

Note:Register 13 ARX bit must be 0 if these bits are used.

2:0ARX[2:0]

Rev. 1.243

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Si3035

D70R/W

D60R/W

D50R/W

D4IIRER/W

D31R/W

D20R/W

D10R/W

D00R/W

Reset settings = 0000_1000Bit7:54

NameReservedIIRE

Function

Read returns zero (must always be written with zeroes).

IIR Filter Enable.0 = FIR filter enabled.

1 = Transmit and receive filters are realized with an IIR filter characteristic. To enable IIR filter write 0x18; to disable IIR filter write 0x08. See Table12 on page11 for more details on IIR fil-ter performance.

Read returns 0x8 (must always be written with 0x8).

3:0Reserved

Register17. International ControlBitNameType

D70

D6MCALR/W

D5CALDR/W

Reset settings = 0000_0000Bit76

NameReservedMCAL

Must be zero.Manual Calibration.0 = No calibration.1 = Initiate calibration.Auto-Calibration.

0 = Auto-calibration enabled.1 = Auto-calibration disabled.Read returns zero.

Function

5CALD

4:0Reserved

44Rev. 1.2

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Si3035

APPENDIX—UL1950 3RD EDITION

Although designs using the Si3035 comply with UL19503rd Edition and pass all overcurrent and overvoltagetests, there are still several issues to consider.

Figure31 shows two designs that can pass the UL1950overvoltage tests, as well as electromagneticemissions. The top schematic of Figure31 shows theconfiguration in which the ferrite beads (FB1, FB2) areon the unprotected side of the sidactor (RV1). For thisconfiguration, the current rating of the ferrite beadsneeds to be 6A. However, the higher current ferritebeads are less effective in reducing electromagneticemissions.

The bottom schematic of Figure31 shows theconfiguration in which the ferrite beads (FB1, FB2) areon the protected side of the sidactor (RV1). For thisdesign, the ferrite beads can be rated at 200mA. In a cost optimized design, it is important to rememberthat compliance to UL1950 does not always requireovervoltage tests. It is best to plan ahead and knowwhich overvoltage tests will apply to your system.System-level elements in the construction, such as fireenclosure and spacing requirements, need to beconsidered during the design stages. Consult with yourprofessional testing agency during the design of theproduct to determine which tests apply to your system.

C2475 Ω @ 100 MHz, 6 A1.25 AFB1TIPRV175 Ω @ 100 MHz, 6 AFB2RINGC25C24600 Ω @ 100 MHz, 200 mAFB11.25 ATIPRV1FB2RING600 Ω @ 100 MHz, 200 mAC25Figure 31. Circuits that Pass all UL1950 Overvoltage TestsRev. 1.2

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Si3035

Pin Descriptions: Si3021

Si3021 (SOIC)

MCLKFSYNCSCLKVDSDOSDIFC/RGDTRESET12345678

161514131211109

OFHKRGDT/FSDM0VAGNDC1AM1AOUT

SDOSDIFC/RGDTRESETAOUTM1C1AGND

Si3021 (TSSOP)

12345678

161514131211109

VDSCLKFSYNCMCLKOFHKRGDT/FSDM0VA

Table 21. Si3021 Pin Descriptions

SOIC TSSOPPin #Pin #1

Pin NameMCLK

Description

Master Clock Input.

High speed master clock input. Generally supplied by the system crystalclock or modem/DSP.

Frame Sync Output.

Data framing signal that is used to indicate the start and stop of acommunication/data frame.

Serial Port Bit Clock Output.

Controls the serial data on SDO and latches the data on SDI.

Digital Supply Voltage.

Provides the digital supply voltage to the Si3021, nominally either 5V or 3.3V.

Serial Port Data Output.

Serial communication data that is provided by the Si3021 to the modem/DSP.Serial Port Data Input.

Serial communication and control data that is generated by the modem/DSP and presented as an input to the Si3021.

Secondary Transfer Request Input/Ring Detect Output.

An optional signal to instruct the Si3021 that control data is being requested in a secondary frame. When daisy chain is enabled, this pin becomes the ring detect output. Produces an active low rectified version of the ring signal.Reset Input.

An active low input that is used to reset all control registers to a defined, ini-tialized state. Also used to bring the Si3034 out of sleep mode.Analog Speaker Output.

Provides an analog output signal for driving a call progress speaker.

214FSYNC

1516

SCLKVD

SDOSDI

73FC/RGDT

84RESET

95AOUT

46Rev. 1.2

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Si3035

Table 21. Si3021 Pin Descriptions (Continued)

SOIC TSSOPPin #Pin #10

Pin Name

Description

Mode Select 1 Input.

The second of two mode select pins that is used to select the operation of the serial port/DSP interface.

Isolation Capacitor 1A.

Connects to one side of the isolation capacitor C1. Used to communicated with the line-side device.

Ground.

Connects to the system digital ground.

Analog Supply Voltage.

Provides the analog supply voltage for the Si3021, nominally 5V. This supply is typically generated internally with an on-chip charge pump set through a control register.

Mode Select 0 Input.

The first of two mode select pins that is used to select the operation of the serial port/DSP interface.

Ring Detect/Delayed Frame Sync Output.

Output signal that indicates the status of a ring signal. Produces an active low rectified version of the ring signal. When daisy chain is enabled, this sig-nal becomes a delayed frame sync to drive a slave device.

Off-Hook Input.

An active low input control signal that provides a termination across TIP and RING for line seizing and pulse dialing.

117C1A

1213

GNDVA

1410M0

1511RGDT/FSD

1612OFHK

Rev. 1.247

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Si3035

Pin Descriptions: Si3012

Si3012 (SOIC or TSSOP)

TSTATSTBIGNDC1BRNG1RNG2QBQE

12345678

161514131211109

TXNCRXREXTDCTHYBDVREG2VREG

Table 22. Si3012 Pin Descriptions

(SOIC or TSSOP)Pin #

Pin NameTSTA

Description

Test Input A.

Allows access to test modes which are reserved for factory use. This pin has aninternal pull-up and should be left as a no connect for normal operation.

Test Input B.

Allows access to test modes which are reserved for factory use. This pin has aninternal pull-up and should be left as a no connect for normal operation.Isolated Ground.

Connects to ground on the line-side interface.Isolation Capacitor 1B.

Connects to one side of isolation capacitor C1.

Ring 1 Input.

Connects through a capacitor to the TIP lead of the telephone line. Provides the ring and caller ID signals to the Si3035.

Ring 2 Input.

Connects through a capacitor to the RING lead of the telephone line. Provides the ring and caller ID signals to the Si3035.

Transistor Base.

Connects to the base of the hookswitch transistor, Q3.Transistor Emitter.

Connects to the emitter of the hookswitch transistor, Q3.

Voltage Regulator.

Connects to an external capacitor to provide bypassing for an internal voltage regulator.

Voltage Regulator 2.

Connects to an external capacitor to provide bypassing for an internal voltage regulator.

2TSTB

345

IGNDC1BRNG1

6RNG2

789

QBQEVREG

10VREG2

48Rev. 1.2

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Si3035

Table 22. Si3012 Pin Descriptions (Continued)

(SOIC or TSSOP)Pin #

111213141516

Pin NameHYBDDCTREXTRXNCTX

Description

Hybrid Node Output.

Balancing capacitor connection used for JATE out-of-band noise support.DC Termination.

Provides DC termination to the telephone network.External Resistor.

Connects to an external resistor.

Receive Input.

Serves as the receive-side input from the telephone network.No Connect.

Transmit Output.

Provides the output through an AC termination impedance to the telephone network.

Rev. 1.249

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Si3035

Ordering Guide

Table 23. Ordering Guide

ChipsetSi3034Si3035Si3036Si3038Si3044Si3044Si3046Si3048

RegionGlobalFCC/JapanFCC/JapanGlobalEnhanced GlobalEnhanced GlobalFCC/JATEGlobal

InterfaceDSP Serial I/FDSP Serial I/FAC LinkAC LinkDSP Serial I/FDSP Serial I/FAC LinkAC Link

Digital(SOIC)Si3021-KSSi3021-KSSi3024-KSSi3024-KSSi3021-KSSi3021-BSSi3025-KSSi3025-KS

Line(SOIC)Si3014-KSSi3012-KSSi3012-KSSi3014-KSSi3015-KSSi3015-BSSi3012-KSSi3014-KS

Digital(TSSOP)Si3021-KTSi3021-KTSi3024-KTSi3024-KT

Line(TSSOP)Si3014-KTSi3012-KTSi3012-KTSi3014-KT

Temperature0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C–40°C to 85°C0°C to 70°C0°C to 70°C

50Rev. 1.2

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Si3035

SOIC Outline

Figure32 illustrates the package details for the Si3021 and Si3012. Table24 lists the values for the dimensionsshown in the illustration.

Figure 32. 16-pin Small Outline Plastic Package (SOIC)

Table 24. Package Diagram Dimensions

Controlling Dimension: mmSymbol

Min

AA1A2bcDEeHLL1γθ

0.0530.0040.0510.0130.0070.3860.1500.050 BSC0.2280.0160.042 BSC

—0°

Inches

Max0.0690.0100.0590.0200.0100.3940.157—0.2440.050—0.0048°

MillimetersMin1.350.101.300.3300.199.803.801.27 BSC5.800.401.07 BSC

—0°

Max1.750.251.500.510.2510.014.00—6.201.27—0.108°

Rev. 1.251

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Si3035

TSSOP Outline

Figure33 illustrates the package details for the Si3021 and Si3014. Table25 lists the values for the dimensionsshown in the illustration.

E1Eθ2R1Rθ1SLL1eθ3DA2AcbA1Figure 33. 16-pin Thin Small Shrink Outline Package (TSSOP)

Table 25. Package Diagram Dimensions

SymbolAA1A2bcDeEE1LL1RR1Sθ1θ2θ3Min—0.050.800.190.094.85MillimetersNom1.10—1.00——5.000.65BSC6.40BSC4.400.601.00 REF————12 REF12 REFMax1.200.151.050.300.205.154.300.450.090.090.2004.500.75———852Rev. 1.2

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Si3035

Data Sheet Changes from Version 1.0 to Version 1.1

Typical Application Circuit was updated.

C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table13. The tolerance was also changed from 20% to 10%.Power Supply Voltage, Analog maximum changed from 4.75V to 5.00V in Table4.

Last paragraph updated in “Power Management” text section.

Data Sheet Changes from Version 1.1 to Version 1.2

!!!!!!!!

TSSOP information added.

Total supply currents updated in Table3 and Table4.Cycle time updated in Table7.

Delay times updated in Table8, Table9, and Table10.

Figure4 updated.

Revision G values added in Table19.

Figure16, “Typical Application Schematic,” on page 15 updated.

Table13, “Component Values—Typical Application,” on page16 (BOM) updated.

Rev. 1.253

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Si3035

Contact Information

Silicon Laboratories Inc.4635 Boston LaneAustin, TX 78735

Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032Email: productinfo@silabs.comInternet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

54Rev. 1.2

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