专利名称：SYSTEM AND METHOD FOR VERIFICATION
AND VALIDATION OF REDUNDANCYSOFTWARE IN PLC SYSTEMS
发明人：Kun Ji,Zhen Song申请号：US13415897申请日：20120309
公开号：US20120246612A1公开日：20120927
专利附图：
摘要：Formal methods are instituted to verify and validate the finite state machine(FSM) of PLC redundancy software. The method and system is implemented through each
phase in the lifecycle of the redundancy software; that is, the requirement phase, designphase, implementation phase and, finally, integration phase (including system
integration). At each step along the way, the verification and validation process uses toolssuch as a checklist-based review and inspection, a requirement traceability analysis,formal verification (model checking) and the like to ensure that the created redundancysoftware is error-free and will perform as intended when implemented in the redundantPLC system.
申请人：Kun Ji,Zhen Song
地址：Plainsboro NJ US,Plainsboro NJ US
国籍：US,US
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