ERROR CORRECTION HARDWARE WITH FAULT DETECTION

专利名称：ERROR CORRECTION HARDWARE WITH

FAULT DETECTION

发明人：SAKET JALAN,INDU PRATHAPAN,ABHISHEK

GANAPATI KARKISAVAL

申请号：US15244739申请日：20160823

公开号：US20180060163A1公开日：20180301

专利附图：

摘要：Error correction code (ECC) hardware includes write generation (Gen) ECC logicand a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC

logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decodeblock coupled to a single bit error correction block. A first MUX receives the write data isin series with an input to the write Gen ECC logic or a second MUX receives the read datafrom the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input ofthe first MUX or for coupling the write data to a second input of the second MUX. An ECCbit comparator compares an output of the write Gen ECC logic to the read Gen ECC logicoutput.

申请人：Texas Instruments Incorporated

地址：Dallas TX US

国籍：US

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