Memory accessing

专利名称：Memory accessing

发明人：Wise, Adrian Philip,Forsyth, Richard Matthew申请号：EP90302343.0申请日：19900306公开号：EP0389142B1公开日：19950712

摘要：A line delay device comprises a memory having RAM cells in two blocks (14,15),each cell being connected to a pair of bit lines. Memory locations in one block (14) areaddressed sequentially and subject to a data transfer while an equate operation iseffected on the bit lines of the other block (15). The operations are switched alternatelybetween the two blocks (14,15). In each accessing cycle a plurality of locations areaddressed in selected rows of each block (14,15) and the switching between each block iseffected without addressing all locations in each row addressed so that the accessingcycle ends in a different block (15) from the starting block (14) and each row used has aplurality of addressed locations.

申请人：INMOS LTD

地址：GB

国籍：GB

代理机构：Palmer, Roger

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