Ordering number : EN5506
Bi-CMOS LSI
LV1100Digital Surround Audio Signal-Processing ICOverview
The LV1100 is an audio signal-processing Bi-CMOS LSIthat integrates input and output filters, a delay line (built-in memory), and a delay/reverb function with a maximumdelay of 120 ms on a single chip. It also provides built-infixed matrix (L+R, L–R) and front mixing (with level andphase switching) functions. A full complement ofsurround modes can be easily implemented by combiningthese functions.
Package Dimensions
unit: mm3067-DIP24S
[LV1100]Functions and Features
•••••••••••
Input switching (L+R, L–R, IN–A)On-chip memory (12K SRAM)
Front adder (+3 dB, 0 dB, –3 dB, -∞)Input and output filters
Input filter –7 kHz low-pass filter
Output filter –5 kHz low-pass filter: switchable with a 3 kHz low-pass filterOn-chip VDDcircuit
Input and output muting function
A simulated surround system can be easily implementedwith only one chip.
ADM A/D and D/A convertersVariable delay times
– Short mode; Maximum delay: 60 ms. Delay timeselectable from six delay times in 10-ms steps.
– Long mode; Maximum delay: 120 ms. Delay timeselectable from six delay times in 20-ms steps.
SANYO: DIP24SSpecifications
Absolute Maximum Ratings at Ta = 25°C
ParameterMaximum supply voltageAllowable power dissipationOperating temperatureStorage temperatureSymbolVCCmaxPd maxToprTstgTa ≤70°CConditionsRatings12420–25 to +70–40 to +125UnitVmW°C°CAllowable Operating Ranges at Ta = 25°C
ParameterRecommended supply voltageOperating supply voltage rangeSymbolVCCVCCopgConditionsRatings98 to 10UnitVVSANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83196HA (OT) No. 5506-1/10
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LV1100
Electrical Characteristics at Ta = 25°C, VCC= 9 V, RL= 20 kΩ, VIN= 300 mV and f = 1 kHz unless otherwise specified.Parameter
Quiescent current
SymbolICCOVOmaxA
Maximum output voltage
VOmaxL
OUT-A, CLOCK FAST, THD = 10%VCC= 8 V
OUT-L, THD = 1% (effect off), VCC= 8 VOUT-A, CLOCK FAST (5 kHz L.P.F)JIS A, Rg = 10 kΩ
OUT-A, CLOCK SLOW (3 kHz L.P.F)JIS A, Rg = 10 kΩ
OUT-L (effect off), JIS A, Rg = 10 kΩOUT-R (effect off), JIS A, Rg = 10 kΩOUT-L (effect –3 dB), JIS A, Rg = 10 kΩOUT-R (effect –3 dB), JIS A, Rg = 10 kΩOUT-A, CLOCK FASTOUT-L (effect off)OUT-R (effect off)
OUT-A, CLOCK FAST (5 kHz L.P.F):400 to 30 kHz BPF
OUT-A, CLOCK SLOW (3 kHz L.P.F):400 to 30 kHz BPF
OUT-L (effect off): 400 to 30 kHz B.P.FOUT-R (effect off): 400 to 30 kHz B.P.F
–4–2–2
Conditions
Ratings
min150.71.61.6
–89–84–103–103–88–880000.30.60.010.01
–80–75–95–95–80–804221.01.50.030.03
typ281.0
max
42
UnitmAVVVdBVdBVdBVdBVdBVdBVdBdBdB%%%%
VOmaxROUT-R, THD = 1% (effect off), VCC= 8 VVNOAFVNOAS
Output noise voltage
VNOLVNORVNOLEVNOREVGA
Output level deviation
VGLVGRTHDAFTHDASTHDLTHDR
Total harmonic distortion
Control Data
Parameter
Control data
Input low-level voltageControl data
Input high-level voltage
SymbolVILVIH
Conditions
Ratings0 to 1.53.5 to 5.5
UnitVV
No. 5506-2/10
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LV1100
Test Circuit
Notes:1.The items D1 through D10 in the figure indicate points that are switched by the serial data.
2.Use capacitors with good high-frequency characteristics for the capacitors on pins 7, 14, and 22. Also, connect 0.1-µF ceramic capacitors inparallel.
Application Circuit Example
Note: The items D1 through D10 in the figure indicate points that are switched by the serial data.
No. 5506-3/10
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LV1100
Block Diagram
Functional Description1.INPUT PHASE SELECT
Selects either the input summation signal (L+R) or the input difference signal (L-R). When set to low, L+R is selected,and when set to high, L-R is selected.
2.INPUT SELECT
Selects either the IN-L and IN-R input signals, or the IN-A input signal.
3.INPUT FILTER
Selects whether the signal input from either IN-L and IN-R or IN-A is passed through a 7-kHz low-pass filter, orwhether it is directly input to the delay block.
4.DELAY
In clock fast mode, creates one of six delayed signals with delays of 10 to 60 ms in 10-ms steps.In clock slow mode, creates one of six delayed signals with delays of 20 to 120 ms in 20-ms steps.
5.VOL (effect volume)
Selects the amount of the front L and R signals added to the delayed signal. Possible settings are +3 dB, 0 dB, –3 dB,and –∞.
6.OUTPUT PHASE SELECT
Selects in-phase (+ setting) or out-of-phase (– setting) with respect to the left channel for the right channel of the VOLoutput signal.
7.REVERVE SW
Set this switch to the on position to specify that the surround system output signal be fed back.8.IN-A OUTPUT FILTER
Allows the signal to be output after passing through a 3-kHz low-pass filter.
No. 5506-4/10
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LV1100
Command List
LV1100 Control Format
A = L ... Selects the LV1100.
B = L ... When B is low, the mode settings listed below can be made.
L
D1D2D3
7 kHz L.P.F ON/OFF
D4, D5LLLHHLHH
THROUGHNOT USEFILTER
A/D INPUT MUTE
L
D6D7D8
OUT-L, –R MUTE ONOUT-A MUTE ONFRONT ADD INPHASE(In-phase addition)
H
OUT-L, –R MUTE OFFOUT-A MUTE OFF
FRONT ADD INVERTED PHASE
(Out-of-phase addition)
IN-A DELAY
L+R
DELAY OUT ON;
Turns on surround system feedback
H
L+R, L–R DELAY
L–R
DELAY OUT OFF;
Turns off surround system feedback
FRONT ADD EFFECT VOL (Addition to the front left and right channels)
D9, D10LLLHHLHH
+3 dB0 dB–3 dBMUTE
B = H ... When B is high, the mode settings listed below can be made.
D1LL
D2LH
IN-A output filter3 kHz L.P.F-OFF3 kHz L.P.F-ON
D3*
D4*
D5*
* = don’t care
No. 5506-5/10
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LV1100
Delay Time Data (D6 to D8)
D6LLLLHH
D7LLHHLL
D8LHLHLH
CLK FAST10 ms20 ms30 ms40 ms50 ms60 ms
CLK SLOW20 ms40 ms60 ms80 ms100 ms120 ms
Note:D6, D7, and D8 must not be used for any purposes other than the above commands.
L
D9D10
SYSTEM MUTE ON
CLK FAST
H
SYSTEM MUTE OFF
CLK SLOW
Control Data Format
•••••
Data is read in on the rising edge of the clock.The control data consists of 12 bits.
The input data is latched on the rising edge of the enable signal.
The clock and enable signals must be held high when not being used to control the LV1100.Command interval time
The timing of intervals between enable signals must meet the conditions shown in the figure.
Notes on Mode Control (System Mute Usage)
1When power is first applied, after the IC is fully operating (about 2 seconds after power is applied) applications mustsend commands that turn the system muting off and then on again.2
Applications must perform system muting on/off operations when switching the delay time or clock fast/slow
settings. After sending a system muting on command along with the new data, send the new data again, this time witha system muting off command.
Note:By performing the operations described in items 1 and 2 here, the memory contents are initialized, thus preventing incorrect operation.
No. 5506-6/10
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LV1100
Data Timing
Timing Characteristics
Parameter
Enable clock delay timeData clock delay timeClock high-level hold timeClock low-level hold timeClock cycle time
Symboltectdctchtcltck
Conditions
Ratings
min
555510
typ
max
Unitµsµsµsµsµs
No. 5506-7/10
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LV1100
Pin Functions
Pin no.1
PinDIGITAL–GND
0 V
Pin voltage
Internal equivalent circuit
2CLK
Control voltage
Apply a voltage of 0 or 5 V.
3DATA
Control voltage
Apply a voltage of 0 or 5 V.
4ENABLE
Control voltage
Apply a voltage of 0 or 5 V.
5REV-OUT
1/2 VCC
6REV-IN
1/2 VCC
Apply the voltage output by pin 5 through an external resistor.
7
VCCVCC(Power-supply voltage)
8IN-L
1/2 VCC
9IN-R
1/2 VCC
10IN-AUX
1/2 VCC
11OUT-AUX
1/2 VCC
12DC-CUT
1/2 VCC
Continued on next page
No. 5506-8/10
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LV1100
Continued from preceding page
Pin no.
Pin
Pin voltage
Internal equivalent circuit
13L.P.F
1/2 VCC
14
VREF1/2 VCC
15OUT-R
1/2 VCC
16OUT-L
1/2 VCC
17ANALOG-GND0 V
18DC-CUT
1/2 VCC
19A/D integrator
1/2 VCC
20A/D noise shaper
1/2 VCC
21D/A integrator
1/2 VCC
22
VDD
5 V
2324
OSCCharged by 0 or 5 V.
No. 5506-9/10
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LV1100
sNo products described or contained herein are intended for use in surgical implants, life-support systems, aerospaceequipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure ofwhich may directly or indirectly cause injury, death or property loss.sAnyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries anddistributors and all their officers and employees, jointly and severally, against any and all claims and litigation and alldamages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation onSANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employeesjointly or severally.
sInformation (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed forvolume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or impliedregarding its use or any infringements of intellectual property rights or other rights of third parties.This catalog provides information as of August, 1996. Specifications and information herein are subject tochange without notice.
No. 5506-10/10
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