基于FPGA的sinc3结构的数字抽取滤波器

基于FPGA的sinc3结构的数字抽取滤波器

基于FPGA的sinc3结构的数字抽取滤波器，今年电子设计大赛D题必用的模块，实测效果非常好，做西格玛-德尔塔ADC必用的滤波器

module sinc3(mdata1, mclk1, reset, DATA ,word_clk,mode); input mclk1; /*滤波器工作时钟*/ input reset; /*滤波器复位*/

input mdata1; /*接收到的待滤波的数据*/ input [1:0]mode;

output [15:0] DATA; /*滤波完成的数据*/ output word_clk;

integer location; integer info_file;

reg [35:0] ip_data1; reg [35:0] acc1; reg [35:0] acc2;

reg [35:0] acc3; reg [35:0] acc3_d1; reg [35:0] acc3_d2; reg [35:0] diff1; reg [35:0] diff2; reg [35:0] diff3; reg [35:0] diff1_d; reg [35:0] diff2_d; reg [15:0] DATA; reg [11:0] word_count;

reg word_clk; reg init;

/*Perform the Sinc ACTION*/ always @ (mdata1) if(mdata1==0)

ip_data1 <= 0; /* change from a 0 to a -1 for 2's comp */ else

ip_data1 <= 1;

/*ACCUMULATOR (INTEGRATOR) Perform the accumulation (IIR) at the

speed of the modulator. Z = one sample delay

MCLKOUT = modulators conversion bit rate*/ always @ (posedge mclk1 or posedge reset) if (reset) begin

/*initialize acc registers on reset*/ acc1 <= 0; acc2 <= 0; acc3 <= 0; end else begin

/*perform accumulation process*/ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end

/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)*/ always @ (negedge mclk1 or posedge reset) if (reset)