AC39LV040 4 Megabit (512K x 8) Flash Memory
Single Power Supply End-of-Program or End-of-Erase Detection − Full voltage range: 2.7 to 3.6 volts for both read − Data# Polling
and write operations − Toggle Bit − Regulated voltage range: 3.0 to 3.6 volts for both read and write operations Sector-Erase Capability CMOS I/O Compatibility Uniform 4Kbyte sectors Read Access Time JEDEC Standard Access time: 45, 55, 70 and 90 ns Pin-out and software command sets compatible with single-power supply Flash memory
Power Consumption High Reliability − Active current: 5 mA (Typical) − Endurance cycles: 100K (Typical) − Standby current: 1 µA (Typical) − Data retention: 10 years Erase/Program Features Package Option − Sector-Erase Time: 40 ms (Typical) − 32-lead PLCC − Chip-Erase Time: 40 ms (Typical) − 32-pin TSOP − Byte-Program Time: 11µs (Typical) − Chip Rewrite Time: 6 seconds (Typical) Automatic Write Timing Internal VPP Generation
PRODUCT DESCRIPTION
The AC39LV040 is a 4M bits Flash memory organized as 512K x 8 bits. The AC39LV040 uses single 3.0 volt-only power supply for both Read and Write functions. Featuring high performance Flash memory technology, the AC39LV040 provides a typical Byte-Program time of 11 µsec and a typical Sector-Erase time of 40 ms. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes. The device offers typical 100,000 cycles endurance and a greater than 10 years data retention. The AC39LV040 conforms to JEDEC standard pin outs for x8 memories. The AC39LV040 is offered in package types of 32-lead PLCC, 32-pin TSOP, and known good die (KGD). For KGD, please contact Actrans System Inc. or its representatives for detailed information.
The AC39LV040 devices are developed for applications that require memories with convenient and economical updating of program, data or configurations, e.g., Networking cards, CD-RW, Scanner, Digital TV, Digital TV, Electronic Books, GPS, Router/Switcher, etc.
Contact Information for Actrans System Inc. 2F, No. 9, Industry E. Rd. IV Science Based Industrial Park Hsinchu 300, Taiwan, R.O.C. Tel. (+886-3) 577-8366 Fax. (+886-3) 577-8369 E-mail. service@actrans-inc.com Website. www.actrans-inc.com This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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ORDERING INFORMATION Standard Products
The order number is defined by a combination of the following elements.
AC39LV040 -70 F W C Description Temperature Range (1 digit) C I E N KGD F = Commercial (0°C to +70°C) = Industrial (-40°C to +85°C) = TSOP (Type 1, die up, 8mm x 14mm) = 32-pin PLCC = Known Good Die (for wafer or dice sell) = PB (Lead) free package AC39LV040
Package Type (1-3 digits) Speed Option (2-3 digits) 45R = 45ns 55 = 55ns 70 = 70ns 90 = 90ns ** = VDD = 2.7~3.6V Full voltage range **R = VDD = 3.0~3.6V Regulated voltage range Device Number/Description AC39LV040 4 Megabit (512K x 8-Bit) Flash Memory
Valid Combinations for TSOP 32Pin Package AC39LV040-45R EC, EI AC39LV040-55 EC, EI AC39LV040-55R EC, EI AC39LV040-70 EC, EI AC39LV040-70R EC, EI AC39LV040-90 EC, EI AC39LV040-90R EC, EI
Valid Combinations for PLCC 32Pin Package AC39LV040-45R NC, NI AC39LV040-55 NC, NI AC39LV040-55R NC, NI AC39LV040-70 NC, NI AC39LV040-70R NC, NI AC39LV040-90 NC, NI AC39LV040-90R NC, NI
Valid Combinations: Valid Combinations list the configurations that are supported in volume for this device.
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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Functional Block Diagram
X-Decoder Address Buffer &Mem ory AddressLatches CE# Control LogicOE# WE#
Pin Assignments
A12A15A16A18VDDWE#A17
1234323130
529A7
628A6
727A5
826A4
32-Lead PLCC925A3 Top View1024A2
1123A1 1222A0 1321DQ014151617181920
AC39LV040
FlashMemory ArrayY-DecoderI/O Buffers and Data LatchesDQ7-DQ0A14A13A8A9A11OE#A10CE#DQ7DQ1DQ2VSSDQ3DQ4DQ5DQ6This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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Pin Assignments
A11A9A8A13A14A17WE#VDDA18A16A15A12A7A6A5A41234567891011121314151632313029282726252423222120191817AC39LV040
Standard TSOPOE#A10CE#DQ7DQ6DQ5DQ4DQ3VSSDQ2DQ1DQ0A0A1A2A3
Table 1. PIN DESCRIPTION
Name of the Pin Function A0–A18 19 addresses DQ7–DQ0 Data inputs/outputs CE# Chip enable OE# Output enable WE# Write enable 3.0 volt-only single power supply* VDD Device ground VSS * Note : see ordering information (page.2) for speed options and voltage supply tolerances
DEVICE OPERATION
The AC39LV040 uses Commands to initiate the memory operation functions. The Commands are written to the device by asserting WE# Low while keeping CE# Low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the AC39LV040 is controlled by CE# and OE#, both have to be Low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram in Figure 1 for further details.
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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Byte Program
AC39LV040
The AC39LV040 is programmed on a byte-by-byte basis. Before programming, the sector where the byte locates must be erased completely. The Program operation is accomplished in three steps. The first step is a three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 16 µs. See Figures 2 and 3 for WE# and CE# controlled Program operation timing diagrams and Figure 12 for flowchart.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
Table 2: AC39LV040 Device Operation
Operation CE# OE# WE# DQ Read VIL VIL VIH DOUT Program VIL VIH VIL DIN
1Erase VIL VIH VIL X Standby VIH X X High Z Write Inhibit X VIL X High Z/DOUT Write Inhibit X X VIH High Z/DOUT Software Mode VIL VIL VIH Product
Identification
Note: X can be VIL or VIH, but no other value.
Address AIN AIN
Sector address, XXH for Chip-Erase
X X X
See Table 3
Write Command/Command Sequence
The AC39LV040 provides two software methods to detect the completion of a Program or Erase cycle in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the write operation is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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Chip Erase
AC39LV040
The AC39LV040 provides Chip-Erase feature, which allows the entire memory array to be erased to logic “1” state. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and Figure 15 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Sector Erase
The AC39LV040 offers Sector-Erase mode. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit method. See Figures 7 for timing waveforms. Any commands issued during the Sector Erase operation are ignored.
Data# Polling (DQ7)
When the AC39LV040 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce the true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Program operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 13 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram and Figure 13 for a flowchart.
Data Protection
The AC39LV040 provides both hardware and software features to protect the data from inadvertent write.
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Hardware Data Protection
AC39LV040
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# Low, CE# High, or WE# High will inhibit the Write operation. This prevents inadvertent write during power-up or power-down.
Software Data Protection (SDP)
The AC39LV040 provides the JEDEC approved Software Data Protection (SDP) scheme for Program
and Erase operations. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, especially during the system power-up or power-down transition. Any Erase operation requires the inclusion of six-byte sequence. See Table 3 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC.
Table 3: Software Command Sequence
Command Sequence
1st Bus Write Cycle
1Addr Data 5555H AAH 5555H AAH 5555H AAH 5555H AAH 2nd Bus Write Cycle
1Addr Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 3rd Bus Write Cycle
1Addr Data 5555H A0H 5555H 80H 5555H 80H 5555H 90H 4th Bus Write Cycle
1Addr Data 2BA Data 5555H AAH 5555H AAH 5th Bus
Write Cycle
1Addr Data 2AAAH 55H 2AAAH 55H 6th Bus
Write Cycle
1Addr Data 3SAX 30H 5555H 10H Byte Program Sector Erase Chip Erase Software ID 4,6
Entry
Manufacture ID 5555H AAH 2AAAH 55H 5555H 90H 0000H 7FH Manufacture ID 5555H AAH 2AAAH 55H 5555H 90H 0003H 7FH Manufacture ID 5555H AAH 2AAAH 55H 5555H 90H 0040H 1FH Device ID 5555H AAH 2AAAH 55H 5555H 90H 0001H 29H 5Software ID Exit XXH F0H 5Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Note:
1. Address format A18-A0 (Hex), Addresses A16 can be VIL or VIH, but no other value, for the Command
sequence.
2. BA = Program byte address.
3. SAX for Sector-Erase; uses A16-A12 address lines.
4. The device does not remain in Software Product ID mode if powered down. 5. Both Software ID Exit operations are equivalent. 6. Please refer to figure 9 for more information.
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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AC39LV040
ABSOLUTE MAXIMUM RATINGS (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ……………….………………………………………………………… –55°C to 125°C
Storage Temperature ……………………….…………………………………..…........………... –65°C to 150°C
D.C. Voltage on Any Pin to Ground Potential ……………………………………………… –0.5 V to VDD+0.5V
Transient Voltage (<20ns) on Any Pin to Ground Potential………………………………. –2.0V to VDD +2.0V Voltage on A9 Pin to Ground Potential…………….……………………..……………………... –0.5 V to 13.2V Package Power Dissipation Capability (Ta=25°C)………………………………..………………………... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds)………………………………………..………. 240°C Output Short Circuit Current (Note 1)…………………………………………………………………….……50mA
Note 1: Output shorted for no more than one second. No more than one output shorted at a time.
Table 4: Operating Range
Model Name AC39LV040
Industrial
Range Commercial
Ambient Temperature 0°C to +70°C -40°C to +85°C
VDD Full voltage range : 2.7~3.6V Regulated voltage range : 3.0~3.6V Full voltage range : 2.7~3.6V Regulated voltage range : 3.0~3.6V AC CONDITIONS OF TEST
Input Rise/Fall Time……………………………………………………………………….5ns
Output Load………………………………………………………………………………..CL=30pF for 45Rns
Output Load………………………………………………………………………………..CL=100pF for 70ns/90ns See Figures 10 and 11
Table 5: DC CHARACTERISTICS (CMOS Compatible)
Parameter Description
IDD Power Supply Current
Read
Program and Erase
ISB Standby VDD Current ILI Input Leakage Current ILO Output Leakage Current VIL Input Low Voltage VIH Input High Voltage VIHC Input High Voltage (CMOS) VOL Output Low Voltage VOH Output High Voltage
Test Conditions
Address Input =VIL/VIH, at f=1/TRC Min, VDD=VDD Max
CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH, CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max
IOL=100µA, VDD=VDD Min IOH=-100µA, VDD=VDD Min
Min 0.7 VDD VDD-0.3
VDD-0.2
Max 20 30 15 1 10 0.8 0.2
Unit mA mA µA µA µA V V V V V
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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Table 6: Recommended System Power-up Timing
AC39LV040
Parameter Description Min Unit
1TPU-READ Power-up to Read Operation 100 µs
1TPU-WRITE Power-up to Program/Erase Operation 100 µs Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 7: Capacitance (Ta=25°C, f=1Mhz, other pins open)
Parameter Description Test Conditions Max
1CI/O I/O Pin Capacitance VI/O=0V 12pF 1CIN Input Capacitance VIN=0V 6pF Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 8: Reliability Characteristics
Symbol Parameter Min Specification Unit Test Method 1NEND Endurance 10,000 Cycles JEDEC Standard A117
1TDR Data Retention 10 Years JEDEC Standard A103
1ILTH Latch Up 100+IDD mA JEDEC Standard 78 Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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AC CCHARACTERISTICS
Table 9: Read Cycle Timing Parameters
Symbol TRC TCE TAA TOE 1TCLZ
1TOLZ 1TCHZ
1TOHZ 1TOH Symbol
Parameter
Read Cycle Time
Chip Enable Access Time Address Access Time
Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change
Parameter
45REC Min Max 45 45 45 30 0 0 15 15 0
55REC Min 55 55 55 30 0 0 15 15 0
70REC Min Max 70 0 70 70 35 0 0 25 25 0
AC39LV040
90REC Max 90 90 90 45 0 0 30 30 0
Unit ns
ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns 55EC 70EC 90EC 45REC
Min Max Min Min Max Max TRC Read Cycle Time 45 55 70 0 90 TCE Chip Enable Access Time 45 55 70 90 TAA Address Access Time 45 55 70 90 TOE Output Enable Access Time 30 30 35 45 1TCLZ CE# Low to Active Output 0 0 0 0 1TOLZ OE# Low to Active Output 0 0 0 0 1TCHZ CE# High to High-Z Output 15 15 25 30 1TOHZ OE# High to High-Z Output 15 15 25 30 1TOH Output Hold from Address Change 0 0 0 0 Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 10: Program/Erase Cycle Timing Parameter
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 1TCPH TDS 1TDH TIDA1 TSE TSCE Parameter
Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector Erase Chip Erase Min 0 30 0 0 0 10 40 40 30 30 40 0 Max 16 150 60 60 Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms Note: This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
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TRCA18~A0TCETAAAC39LV040
CE#OE#TOEVIHWE#TOLZTOHZTCLZTOHData ValidTCHZData ValidHIGH-ZHIGH-ZDQ7-0Figure 1. Read Cycle Timing Diagram
Internal Program Operation StartsTBP5555TAHWE#TWPA18~A02AAA5555ADDRTDHTWPHTASOE#TDSCE#DQ7-0 TCS AA55A0DATA SW0SW1SW2Byte (ADDR/DATA)
Figure 2. WE# Controlled Program Cycle Timing Diagram
TCH This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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AC39LV040
Internal Program Operation StartsTBPA18~A05555TAHTCPCE#TCPHTASOE#TDS2AAA5555ADDRTDHTCHWE#TCSDQ7-0AASW055SW1A0SW2DATAByte(ADDR/DATA)Figure 3. CE# Controlled Program Cycle Timing Diagram
A18~A0TCECE#TOEHOE#TOEWE#TOESDQ7DATADATA#DATA#DATA# Figure 4. Data# Polling Timing Diagram
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A18~A0
TCECE#
TOEHOE#
TOEAC39LV040
TOESWE#
DQ6
Figure 5. Toggle Bit Timing Diagram
Two Read CyclesWith Same Outputs
Six-Byte Code For Chip-EraseTSCE5555A18~A055552AAA555555552AAACE#OE#TWPWE# AAAA55805510DQ7-0 SW0SW1SW2SW3SW4SW5 Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 10)
Figure 6. WE# Controlled Chip-Erase Timing Diagram
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AC39LV040
Six-Byte Code For Sector-EraseTSESAXA18~A055552AAA555555552AAACE#OE#TWWE#PDQ7-0AASW055SW180SW2AASW355SW430SW5Note: This device also supports CE# controlled Sector-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 10)SAX=SectorAddressX can be VILor V Figure 7. WE# Controlled Sector-Erase Timing Diagram
IH, but no other value. Three-Byte Sequence ForSoftware ID EntryAddress A14-055552AAA55550000H0003H0040H0001HCE#OE#TWPWE#TWPHDQ7-0AASW055SW190SW2TAA7F7F1F29hTIDAFigure 8. Software ID Entry and Read
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Three-Byte Sequence ForSoftware ID Exit and ResetAC39LV040
Address A14-055552AAA5555DQ7-0AA55F0TIDACE#OE#TWPWE#SW0TWPHSW1SW2Figure 9. Software ID Exit and Reset
VIHTInputVILTVIT Reference Points VOTOutput AC test inputs are driven at VIHT (0.9 VDD) for a logic \"1\" and VILT(0.1 VDD) for a logic \"0\".Measurement reference points for inputs and outpputs are VIT(0.5 VDD) and VOT(0.5 VDD). Input rise and fall times(10% - 90% ) are <5ns
Note: VIT = Vinput Test VOT = Voutput Test VIHT = Vinput HIGH Test VILT = Vinput LOW TestFigure 10. AC Input/Output Reference Waveforms
This preliminary data sheet contains product specifications which are subject to change without notice. Rev. 1.0 (6/29/04)
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AC39LV040
TO TESTERTO DUTCL
Figure 11. A Test Load Example
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Program CompletedWait for end of Program(TBP, Data# Polling bit, orToggle bit operation)Load ByteAddress/Byte DataLoad Data: A0HAddress: 5555HLoad Data: 55HAddress: 2AAAHLoad Data: AAHAddress: 5555HStartAC39LV040
Figure 12. Byte-Program Algorithm
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Figure 20. Temporary Sector Unprotect Timing Diagram
Internal TimerProgrm/EraseInitiatedToggle BitAC39LV040
Data# PollingProgrm/EraseInitiatedProgrm/Erase Initiated Wait TBP, TSCE,TSE or TBERead Byte Read DQ7Progrm/EraseCompletedRead SameByteIs DQ7=truedata?YesNoProgrm/EraseCompletedNoDoes DQ6match? YesProgrm/Erase CompletedFigure 13. Wait Options
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Software ID EntryCommand SequenceLoad Data: AAHAddress: 5555HSoftware ID Exit Command SequenceAC39LV040
Load Data: AAH Address: 5555HLoad Data: F0HAddress: XXH Load Data: 55HAddress: 2AAAHLoad Data: 55HAddress: 2AAAHWait TIDA Load Data: 90HAddress: 5555HLoad Data: F0HAddress: 55 55HReturn to NormalOperationWait TIDAWait TIDA Read Software IDReturn to NormalOperation X can be VIL or VIH, but no other value.
Figure 14. Software ID Command Flowcharts
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Chip-EraseCommand SequenceAC39LV040
Sector-EraseCommand SequenceLoad Data: AAHAddress: 5555HLoad Data: AAHAddress: 5555HLoad Data: 55HAddress: 2AAAHLoad Data: 55HAddress: 2AAAHLoad Data: 80HAddress: 5555H Load Data: 80HAddress: 5555HLoad Data: AAHAddress: 5555H Load Data: AAHAddress: 5555HLoad Data: 55HAddress: 2AAAHLoad Data: 55HAddress: 2AAAHLoad Data: 10HAddress: 5555HLoad Data: 30HAddress: SAXWait TSCEWait T SEChip Erased to FFH Sector Erased to FFH X can be VIL or VIH, but no other value.
Figure 15. Erase Command Sequence
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