Virtex®-5 devices have six configuration interfaces. Each configuration interface
corresponds to one or more configuration modes and bus width, shown in Table2-1. For detailed interface timing information, see DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristic.
Table 2-1:Virtex-5 Device Configuration Modes
Configuration ModeMaster Serial(2)Master SPI(2)Master BPI-Up(2)Master BPI-Down(2)Master SelectMAP(2)JTAG
Slave SelectMAPSlave Serial
Notes:
1.Parallel configuration mode bus is auto-detected by the configuration logic.
2.In Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the
internal configuration logic. Refer to the “Board Layout for Configuration Clock (CCLK)” section formore details.
M[2:0]000001010011100101110111
Bus Width
118, 168, 168, 1618, 16, 321
CCLK Direction
OutputOutputOutputOutputOutputInput (TCK)InputInput
Serial Configuration Interface
In serial configuration modes, the FPGA is configured by loading one configuration bit per CCLK cycle:
In Master Serial mode, CCLK is an output.In Slave Serial mode, CCLK is an input.
Figure2-1 shows the basic Virtex-5 serial configuration interface.There are four methods of configuring an FPGA in serial mode:
Master serial configurationSlave serial configurationSerial daisy-chain configuration
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Byte Peripheral Interface Parallel Flash Mode
Table 2-9:Virtex-5 Device BPI Configuration Interface Pins (Continued)
Type
Dedicated or Dual-Purpose
Description
Pin Name INIT_B
Input or Dedicated Before the Mode pins are sampled, INIT_B is an input that can be held Output, Low to delay configuration. After the Mode pins are sampled, INIT_B Open-Drain is an open-drain, active-Low output indicating whether a CRC error
occurred during configuration:
0 = CRC error 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected.
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset
CCLK Output
Dedicated Configuration clock output. CCLK does not directly connect to BPI
Flash but is used internally to generate the address and sample read data. Dual
Active-Low Flash chip select output. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash output enable. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash write enable. This output is actively driven High during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Address output. For I/O bank locations, see Table1-2, page17.
FCS_BOutput
FOE_B Output Dual
FWE_BOutputDual
ADDR[25:0]OutputDual
D[15:0]InputDual
Data input, sampled by the rising edge of the FPGA CCLK. For I/O bank location, see Table1-2, page17.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 3:Boundary-Scan and JTAG Configuration
Capture-DR:
In this controller state, the data is parallel-loaded into the data registers selected by the current instruction on the rising edge of TCK.
Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.
10TEST-LOGIC-RESET0RUN-TEST/IDLE1SELECT-DR-SCAN10CAPTURE-DR0SHIFT-DR1EXIT1-DR0PAUSE-DR01EXIT2-DR1UPDATE-DR10100101SELECT-IR-SCAN10CAPTURE-IR0SHIFT-IR1EXIT1-IR0PAUSE-IR1EXIT2-IR1UPDATE-IR00101NOTE: The value shown adjacent to each state transition in this figurerepresents the signal present at TMS at the time of a rising edge at TCK.
UG191_c3_02_050406
Figure 3-2:Boundary-Scan TAP Controller
Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.
The Virtex-5 Boundary-Scan operations are independent of mode selection. The
Boundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason, Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a Virtex-5 device is configured. After configuration, all instructions are available.
JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture and
configuration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.
For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
因篇幅问题不能全部显示，请点此查看更多更全内容