专利名称：Microprocessor architecture employing
efficient operand and instruction addressing
发明人：Philip F. Kromer, III申请号：US06/304017申请日：19810921公开号：US04541045A公开日：19850910
摘要：A two-bus, two instruction type, pipelined microprocessor having a controlmeans which orders application of instruction and data addresses to a memory andfurther interleaves instructions and data on a single bus to achieve maximum efficiency inoperation.
申请人：RACAL-MILGO, INC.
代理机构：Jackson & Jones
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