LM20133 3A, PowerWise® Synchronous Buck Regulator with Input SynchronizationNovember 13, 2007
LM20133
3A, PowerWise® Synchronous Buck Regulator with InputSynchronization
General Description
The LM20133 is a full featured synchronous buck regulatorcapable of delivering up to 3A of continuous output current.The current mode control loop can be compensated to bestable with virtually any type of output capacitor. For mostcases, compensating the device only requires two externalcomponents, providing maximum flexibility and ease of use.The device is optimized to work over the input voltage rangeof 2.95V to 5.5V making it suited for a wide variety of low volt-age systems.
The device features internal over voltage protection (OVP)and over current protection (OCP) circuits for increased sys-tem reliability. A precision enable pin and integrated UVLOallows the turn on of the device to be tightly controlled andsequenced. Start-up inrush currents are limited by both aninternally fixed and externally adjustable Soft-Start circuit.Fault detection and supply sequencing is possible with theintegrated power good circuit.
The switching frequency of the LM20133 can be synchro-nized to an external clock by use of the SYNC pin. The SYNCpin is capable of synchronizing to input signals ranging from500 kHz to 1.5 MHz.
The LM20133 is designed to work well in multi-rail powersupply architectures. The output voltage of the device can beconfigured to track a higher voltage rail using the SS/TRK pin.If the output of the LM20133 is pre-biased at startup it will notsink current to pull the output low until the internal soft-startramp exceeds the voltage at the feedback pin.
The LM20133 is offered in a 16-pin eTSSOP package with anexposed pad that can be soldered to the PCB, eliminating theneed for bulky heatsinks.
Features
Input voltage range 2.95V to 5.5V
Accurate current limit minimizes inductor size97% peak efficiency
Frequency synchronization pin32 mΩ integrated FET switchesStarts up into pre-biased loadsOutput voltage trackingPeak current mode control
Adjustable Soft-Start with external capacitorPrecision enable pin with hysteresis
Integrated OVP, UVLO, power good and thermalshutdown
■eTSSOP-16 exposed pad package
■■■■■■■■■■■
Applications
■Simple to design, high efficiency point of load regulation
from a 5V or 3.3V bus
■High Performance DSPs, FPGAs, ASICs andmicroprocessors
■Broadband, Networking and Optical CommunicationsInfrastructure
Typical Application Circuit
30030301
PowerWise® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation300303www.national.com
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LM20133Connection Diagram
Top View
eTSSOP-16 Package
30030302
Ordering Information
Order NumberLM20133MHLM20133MHELM20133MHX
Package TypeeTSSOP-16
NSC Package Drawing
MXA16A
Package Marking
20133MH
Supplied As92 Units of Rail250 Units of Tape and Reel2500 Units of Tape and Reel
Pin Descriptions
Pin #1
NameSS/TRK
Description
Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor toset the Soft-Start ramp rate. If driven by a external source less than 800 mV, this pin overrides theinternal reference that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated.Feedback input to the error amplifier from the regulated output. This pin is connected to the invertinginput of the internal transconductance error amplifier. An 800mV reference connected to the non-inverting input of the error amplifier sets the closed loop regulation voltage at the FB pin.Power good output signal. Open drain output indicating the output voltage is regulating withintolerance. A pull-up resistor of 10 to 100 kΩ is recommend for most applications.
External compensation pin. Connect a resistor and capacitor to this pin to compensate the device.These pins must be connected to GND to ensure proper operation.
Input voltage to the power switches inside the device. These pins should be connected together at thedevice. A low ESR capacitor should be placed near these pins to stabilize the input voltage.Switch pin. The PWM output of the internal power switches.Power ground pin for the internal power switches.
Precision enable input for the device. An external voltage divider can be used to set the device turn-on threshold. If not used the EN pin should be connected to PVIN.
Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor.
Analog input supply that generates the internal bias. Must be connected to VIN through a low passRC filter.
Quiet analog ground for the internal bias circuitry.
Frequency synchronization pin. An external clock connected to this pin will set the switching frequency.If left open the device will switch at approximately 410 kHz.
Exposed metal pad on the underside of the package with a weak electrical connection to ground. It isrecommended to connect this pad to the PC board ground plane in order to improve heat dissipation.
2FB
3456,78,910,111213141516EP
PGOODCOMPNCPVINSWPGNDENVCCAVINAGNDSYNCExposed Pad
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LM20133Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Voltages from the indicated pins to GNDAVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, SW, SYNCStorage TemperatureJunction Temperature
-0.3V to +6V-65°C to 150°C
150°C
Power Dissipation (Note 2)Lead Temperature (Soldering,10 sec)
Minimum ESD Rating (Note 3)
2.6W260°C±2kV
Operating Ratings
PVIN, AVIN to GNDJunction Temperature
2.95V to 5.5V−40°C to + 125°C
Electrical Characteristics
Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V.
Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent themost likely parametric norm at TJ = 25°C, and are provided for reference purposes only.SymbolVFBΔVOUT/ΔIOUT
ICLRDS_ONRDS_ON
IQISDVUVLOVUVLO_HYS
VVCCISSVTRACK
Oscillator
FOSCFOSCHFOSCLVIH_SYNCVIL_SYNCISYNCTOFF_TIMETON_TIMETCL_BLANK
IFBICOMP_SRCICOMP_SNK
gmAVOL
Power Good
VOVPVOVP_HYSVPGTHVPGHYSTPGOODIOLIOH
Over Voltage Protection Rising ThresholdOver Voltage Protection HysteresisPGOOD Rising ThresholdPGOOD Falling HysteresisPGOOD deglitch timePGOOD Low Sink CurrentPGOOD High Leakage Current
VPGOOD = 0.4VVPGOOD = 5V
3
Parameter
Feedback pin voltageLoad Regulation
Switch Current Limit ThresholdHigh-Side Switch On ResistanceLow-Side Switch On ResistanceOperating Quiescent CurrentShutdown Quiescent currentVIN Under Voltage Lockout
VIN Under Voltage Lockout HysteresisVCC Voltage
Soft-Start Pin Source CurrentSS/TRK Accuracy, VSS - VFBOscillator Frequency
Maximum External SYNC FrequencyMinimum External SYNC FrequencySYNC pin Logic HighSYNC pin Logic LowSYNC pin input leakageMinimum Off TimeMinimum On Time
Current Sense Blanking TimeFeedback pin bias currentCOMP Output Source CurrentCOMP Output Sink CurrentError Amplifier TransconductanceError Amplifier Voltage Gain
ConditionsVIN = 2.95V to 5.5VIOUT = 100 mA to 3AVIN = 3.3VISW = 3.5AISW = 3.5A
Non-switching, VFB = VCOMPVEN = 0VRising VINFalling VINIVCC = 0 µAVSS/TRK = 0VVSS/TRK = 0.4V
No External SYNC Signal
VSYNC = 5V
After Rising VSWVFB = 0.8VVFB = VCOMP = 0.6VVFB = 1.0V, VCOMP = 0.6VICOMP = ± 50 µA
With respect to VFBWith respect to VFB
Min0.788 4.7 2.45 2.452-10360 4602 8080450 105 92 0.6
Typ0.80.085.236323.5902.7452.74.534101500 1085100801100100510200010829421615
Max0.812 5.7555261802.951002.95715460 0.8 100 600
UnitV%/AAmΩmΩmAµAVmVVµAmVkHzkHzkHzVVnAnsnsnsnAµAµAµmhoV/V
Error Amplifier and Modulator
1113963 100
%%%%µsmAnA
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LM20133SymbolEnable
VIH_ENVEN_HYSTSDTSD_HYSθJA
Parameter
EN Pin Turn on ThresholdEN Pin HysteresisThermal Shutdown
Thermal Shutdown HysteresisJunction to Ambient
ConditionsVEN Rising
Min1.08
Typ1.18661601038
Max1.28
UnitVmV°C°C°C/W
Thermal Shutdown
Thermal Resistance
Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isintended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.Note 2:The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal resistance, θJA,and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA)/θJA. Themaximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C.Note 3:The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.
Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH
(Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots andwaveforms, and TJ = 25°C for all others.
Efficiency vs. Load Current (VIN = 5V, fSW = 1.5 MHz)
Efficiency vs. Load Current (VIN = 3.3V, fSW = 1.5 MHz)
Typical Performance Characteristics
30030331
30030330
Efficiency vs. Load Current (VIN = 5V, fSW = 1 MHz)Efficiency vs. Load Current (VIN = 3.3V, fSW = 1 MHz)
3003034730030346
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LM20133Efficiency vs. Load Current (VIN = 5V, fSW = 500 kHz)Efficiency vs. Load Current (VIN = 3.3V, fSW = 500 kHz)
3003034930030348
High-Side FET resistance vs. TemperatureLow-Side FET resistance vs. Temperature
3003035230030353
Error Amplifier Gain vs. FrequencyLine Regulation
3003033630030337
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LM20133Load RegulationFeedback Voltage vs. Temperature
3003033830030351
Switching Frequency vs. TemperatureSwitch Synchronization
30030360
30030339
Quiescent Current vs. VIN (Not Switching)
Shutdown Current vs. Temperature
3003034030030341
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LM20133Enable Threshold vs. TemperatureUVLO Threshold vs. Temperature
3003032830030345
Peak Current Limit vs. Temperature
Peak Current Limit vs. VOUT
3003034230030354
Peak Current Limit vs. VIN
Load Transient Response
30030334
30030356
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LM20133Line Transient ResponseStart-Up (Soft-Start)
3003034330030344
Start-Up (Tracking)Power Down
30030333
30030332
Short Circuit Input Current vs. VINPGOOD vs. IPGOOD
3003035530030327
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LM20133Block Diagram
30030303
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LM20133Operation Description
GENERAL
The LM20133 switching regulator features all of the functionsnecessary to implement an efficient low voltage buck regula-tor using a minimum number of external components. Thiseasy to use regulator features two integrated switches and iscapable of supplying up to 3A of continuous output current.The regulator utilizes peak current mode control with nonlin-ear slope compensation to optimize stability and transientresponse over the entire output voltage range. Peak currentmode control also provides inherent line feed-forward, cycle-by-cycle current limiting and easy loop compensation. Theinternal oscillator can synchronize up to 1.5 MHz minimizingthe inductor size while still achieving efficiencies up to 96%.The precision internal voltage reference allows the output tobe set as low as 0.8V. Fault protection features include: cur-rent limiting, thermal shutdown, over voltage protection, andshutdown capability. The device is available in theeTSSOP-16 package featuring an exposed pad to aid thermaldissipation. The LM20133 can be used in numerous applica-tions to efficiently step-down from a 5V or 3.3V bus. Thetypical application circuit for the LM20133 is shown in Figure2.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be en-abled or disabled with an external control signal. This pin is aprecision analog input that enables the device when the volt-age exceeds 1.18V (typical). The EN pin has 66 mV of hys-teresis and will disable the output when the enable voltagefalls below 1.11V (typical). If the EN pin is not used, it shouldbe connected to VIN. Since the enable pin has a precise turnon threshold it can be used along with an external resistordivider network from VIN to configure the device to turn on ata precise input voltage. The precision enable circuitry will re-main active even when the device is disabled.
FREQUENCY SYNCHRONIZATION
The frequency synchronization pin (SYNC) allows the switch-ing frequency of the device to be controlled with an externalclock signal. This feature allows the user to synchronize mul-tiple converters, avoiding undesirable frequency bands ofoperation. When used with the SYNCOUT of the LM20154,multiple devices can be configured to switch out of phase re-ducing input capacitor requirements and EMI of the powersupply system.
The turn on of the high side switch will lock-on to the risingedge of the SYNC pin input. The logic low level for the inputclock must be below 0.8V and the logic high level must exceed2.0V to guarantee proper operation. The device will synchro-nize to frequencies from 500 kHz to 1.5 MHz. If the synchro-nization clock is removed or not present during startup, theoscillator of the device will run at approximately 410 kHz. Ifthe SYNC pin is not used it should be connected to ground.PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architectureused in the LM20133 only requires two external componentsto achieve a stable design. The compensation can be select-ed to accommodate any capacitor type or value. The externalcompensation also allows the user to set the crossover fre-quency and optimize the transient performance of the device.For duty cycles above 50% all current mode control buckconverters require the addition of an artificial ramp to avoidsub-harmonic oscillation. This artificial linear ramp is com-
monly referred to as slope compensation. What makes theLM20133 unique is the amount of slope compensation willchange depending on the output voltage. When operating athigh output voltages the device will have more slope com-pensation than when operating at lower output voltages. Thisis accomplished in the LM20133 by using a non-linearparabolic ramp for the slope compensation. The parabolicslope compensation of the LM20133 is much better than thetraditional linear slope compensation because it optimizes thestability of the device over the entire output voltage range.CURRENT LIMIT
The precise current limit of the LM20133 is set at the factoryto be within 10% over the entire operating temperature range.This enables the device to operate with smaller inductors thathave lower saturation currents. When the peak inductor cur-rent reaches the current limit threshold, an over current eventis triggered and the internal high-side FET turns off and thelow-side FET turns on allowing the inductor current to rampdown until the next switching cycle. For each sequential over-current event, the reference voltage is decremented andPWM pulses are skipped resulting in a current limit that doesnot aggressively fold back for brief over-current events, whileat the same time providing frequency and voltage foldbackprotection during hard short circuit conditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to setthe start up time or track an external voltage source. The startup or Soft-Start time can be adjusted by connecting a capac-itor from the SS/TRK pin to ground. The Soft-Start featureallows the regulator output to gradually reach the steady stateoperating point, thus reducing stresses on the input supplyand controlling start up current. If no Soft-Start capacitor isused the device defaults to the internal Soft-Start circuitry re-sulting in a start up time of approximately 1 ms. For applica-tions that require a monotonic start up or utilize the PGOODpin, an external Soft-Start capacitor is recommended. TheSS/TRK pin can also be set to track an external voltagesource. The tracking behavior can be adjusted by two externalresistors connected to the SS/TRK pin as shown in Figure 7in the design guide.
PRE-BIAS START UP CAPABILITY
The LM20133 is in a pre-biased state when the device startsup with an output voltage greater than zero. This often occursin many multi-rail applications such as when powering an FP-GA, ASIC, or DSP. In these applications the output can bepre-biased through parasitic conduction paths from one sup-ply rail to another. Even though the LM20133 is a syn-chronous converter it will not pull the output low when a pre-bias condition exists. During start up the LM20133 will not sinkcurrent until the Soft-Start voltage exceeds the voltage on theFB pin. Since the device can not sink current it protects theload from damage that might otherwise occur if current isconducted through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLINGThe LM20133 has built in under and over voltage compara-tors that control the power switches. Whenever there is anexcursion in output voltage above the set OVP threshold, thepart will terminate the present on-pulse, turn-on the low sideFET, and pull the PGOOD pin low. The low side FET will re-main on until either the FB voltage falls back into regulationor the zero cross detection is triggered which in turn tri-statesthe FETs. If the output reaches the UVP threshold the part willcontinue switching and the PGOOD pin will be asserted and
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LM20133go low. Typical values for the PGOOD resistor are on the or-der of 100 kΩ or less. To avoid false tripping during transientglitches the PGOOD pin has 16 µs of built in deglitch time toboth rising and falling edges.
UVLO
The LM20133 has a built-in under-voltage lockout protectioncircuit that keeps the device from switching until the inputvoltage reaches 2.7V (typical). The UVLO threshold has 45mV of hysteresis that keeps the device from responding topower-on glitches during start up. If desired the turn-on pointof the supply can be changed by using the precision enablepin and a resistor divider network connected to VIN as shownin Figure 6 in the design guide.
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect theintegrated circuit in the event that the maximum junction tem-perature is exceeded. When activated, typically at 160°C, theLM20133 tri-states the power FETs and resets soft start. Afterthe junction cools to approximately 150°C, the part starts upusing the normal start up routine. This feature is provided toprevent catastrophic failures from accidental device over-heating.
LIGHT LOAD OPERATION
The LM20133 offers increased efficiency when operating atlight loads. Whenever the load current is reduced to a pointwhere the inductor ripple current is greater than two times theload current, the part will enter the diode emulation modepreventing significant negative inductor current. The point atwhich this occurs is the critical conduction boundary and canbe calculated by the following equation:
Several diagrams are shown in Figure 1 illustrating continu-ous conduction mode (CCM), discontinuous conductionmode, and the boundary condition.
It can be seen that in diode emulation mode, whenever theinductor current reaches zero the SW node will become highimpedance. Ringing will occur on this pin as a result of the LCtank circuit formed by the inductor and the parasitic capaci-tance at the node. If this ringing is of concern an additionalRC snubber circuit can be added from the switch node toground.
At very light loads, usually below 100 mA, several pulses maybe skipped in between switching cycles, effectively reducingthe switching frequency and further improving light-load effi-ciency.
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LM2013330030305
FIGURE 1. Modes of Operation for LM20133
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LM20133Design Guide
This section walks the designer through the steps necessaryto select the external components to build a fully functionalpower supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size, orperformance. These will be taken into account and highlight-ed throughout this discussion. To facilitate component selec-tion discussions the circuit shown in Figure 2 below may beused as a reference. Unless otherwise indicated all formulasassume units of amps (A) for current, farads (F) for capaci-tance, henries (H) for inductance and volts (V) for voltages.
30030309
FIGURE 3. Switch and Inductor Current WaveformsIf needed, slightly smaller value inductors can be used, how-ever, the peak inductor current, IOUT + ΔiL/2, should be keptbelow the peak current limit of the device. In general, the in-ductor ripple current, ΔiL, should be greater than 10% of therated output current to provide adequate current sense infor-mation for the current mode control loop. If the ripple currentin the inductor is too low, the control loop will not have suffi-cient current sense information and can be prone to instability.OUTPUT CAPACITOR SELECTION (COUT)
The output capacitor, COUT, filters the inductor ripple currentand provides a source of charge for transient load conditions.A wide range of output capacitors may be used with theLM20123 that provide excellent performance. The best per-formance is typically obtained using ceramic, SP, or OSCONtype chemistries. Typical trade-offs are that the ceramic ca-pacitor provides extremely low ESR to reduce the outputripple voltage and noise spikes, while the SP and OSCONcapacitors provide a large bulk capacitance in a small volumefor transient loading conditions.
When selecting the value for the output capacitor the two per-formance characteristics to consider are the output voltageripple and transient response. The output voltage ripple canbe approximated by using the formula shown below.
30030323
FIGURE 2. Typical Application Circuit
The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETsand parasitic resistances it can be approximated by:
INDUCTOR SELECTION (L)
The inductor value is determined based on the operating fre-quency, load current, ripple current, and duty cycle. Theinductor selected should have a saturation current ratinggreater than the peak current limit of the device. Keep in mindthe specified current limit does not account for delay of thecurrent limit comparator, therefore the current limit in the ap-plication may be higher than the specified value. To optimizethe performance and prevent the device from entering currentlimit at maximum load, the inductance is typically selectedsuch that the ripple current, ΔiL, is less than 30% of the ratedoutput current. Figure 3, shown below illustrates the switchand inductor ripple current waveforms. Once the input volt-age, output voltage, operating frequency, and desired ripplecurrent are known, the minimum value for the inductor can becalculated by the formula shown below:
Where, ΔVOUT (V) is the amount of peak to peak voltage rippleat the power supply output, RESR (Ω) is the series resistanceof the output capacitor, fSW(Hz) is the switching frequency,and COUT (F) is the output capacitance used in the design.The amount of output ripple that can be tolerated is applica-tion specific; however a general recommendation is to keepthe output ripple less than 1% of the rated output voltage.Keep in mind ceramic capacitors are sometimes preferredbecause they have very low ESR; however, depending onpackage and voltage rating of the capacitor the value of thecapacitance can drop significantly with applied voltage. Theoutput capacitor selection will also affect the output voltagedroop during a load transient. The peak droop on the outputvoltage during a load transient is dependent on many factors;however, a best case approximation of the transient droopignoring loop bandwidth can be obtained using the followingequation.
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LM20133Where, COUT (F) is the minimum required output capacitance,L (H) is the value of the inductor, VDROOP (V) is the outputvoltage drop ignoring loop bandwidth considerations, ΔIOUT-STEP (A) is the load step change, RESR (Ω) is the outputcapacitor ESR, VIN (V) is the input voltage, and VOUT (V) isthe set regulator output voltage. Both the tolerance and volt-age coefficient of the capacitor needs to be examined whendesigning for a specific output ripple or transient drop target.INPUT CAPACITOR SELECTION (CIN)
Good quality input capacitors are necessary to limit the ripplevoltage at the VIN pin while supplying most of the switch cur-rent during the on-time. In general it is recommended to usea ceramic capacitor for the input as they provide both a lowimpedance and small footprint. One important note is to usea good dielectric for the ceramic capacitor such as X5R orX7R. These provide better over temperature performanceand minimize the DC voltage derating that occurs on Y5V ca-pacitors. For most applications, a 22 µF, X5R, 6.3V inputcapacitor is sufficient; however, additional capacitance maybe required if the connection to the input supply is far from thePVIN pins. The input capacitor should be placed as close aspossible PVIN and PGND pins of the device.
Non-ceramic input capacitors should be selected for RMScurrent rating and minimum ripple voltage. A good approxi-mation for the required ripple current rating is given by therelationship:
LOOP COMPENSATION (RC1, CC1)
The purpose of loop compensation is to meet static and dy-namic performance requirements while maintaining adequatestability. Optimal loop compensation depends on the outputcapacitor, inductor, load, and the device itself. Table 2 belowgives values for the compensation network that will result ina stable system when using a 100 µF, 6.3V ceramic X5R out-put capacitor and 1 µH inductor.
TABLE 2. Recommended Compensation forCOUT = 100 µF, L = 1 µH & fSW = 1 MHz
VIN5.005.005.005.005.005.003.303.303.303.30
VOUT3.302.501.801.501.200.801.801.501.200.80
CC1 (nF)RC1 (kΩ)4.74.74.74.74.74.74.74.74.74.7
16.211.38.455.233.321.629.534.873.241.62
As indicated by the RMS ripple current equation, highest re-quirement for RMS current rating occurs at 50% duty cycle.For this case, the RMS ripple current rating of the input ca-pacitor should be greater than half the output current. For bestperformance, low ESR ceramic capacitors should be placedin parallel with higher capacitance capacitors to provide thebest input filtering for the device.
SETTING THE OUTPUT VOLTAGE (RFB1, RFB2)
The resistors RFB1 and RFB2 are selected to set the outputvoltage for the device. Table 1, shown below, provides sug-gestions for RFB1 and RFB2 for common output voltages.
TABLE 1. Suggested Values for RFB1 and RFB2
RFB1(kΩ)short4.998.8712.721.531.6
RFB2(kΩ)open1010.210.210.210.2
VOUT0.81.21.51.82.53.3
If the desired solution differs from the table above the looptransfer function should be analyzed to optimize the loopcompensation. The overall loop transfer function is the prod-uct of the power stage and the feedback network transferfunctions. For stability purposes, the objective is to have aloop gain slope that is -20db/decade from a very low frequen-cy to beyond the crossover frequency. Figure 4, shown below,shows the transfer functions for power stage, feedback/com-pensation network, and the resulting closed loop system forthe LM20133.
If different output voltages are required, RFB2 should be se-lected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can becalculated using the equation below.
30030313
FIGURE 4. LM20133 Loop Compensation
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LM20133The power stage transfer function is dictated by the modula-tor, output LC filter, and load; while the feedback transferfunction is set by the feedback resistor ratio, error amp gain,and external compensation network.
To achieve a -20dB/decade slope, the error amplifier zero,located at fZ(EA), should positioned to cancel the output filterpole (fP(FIL)). An additional error amp pole, located at fP2(EA),can be added to cancel the output filter zero at fZ(FIL). Can-cellation of the output filter zero is recommended if largervalue, non-ceramic output capacitors are used.
Compensation of the LM20133 is achieved by adding an RCnetwork as shown in Figure 5 below.
AVIN FILTERING COMPONENTS (CF and RF)
To prevent high frequency noise spikes from disturbing thesensitive analog circuitry connected to the AVIN and AGNDpins, a high frequency RC filter is required between PVIN andAVIN. These components are shown in Figure 2 as CF andRF. The required value for RF is 1Ω. CF must be used. Rec-ommended value of CF is 1.0 µF. The filter capacitor, CFshould be placed as close to the IC as possible with a directconnection from AVIN to AGND. A good quality X5R or X7Rceramic capacitor should be used for CF.
SUB-REGULATOR BYPASS CAPACITOR (CVCC)
The capacitor at the VCC pin provides noise filtering and sta-bility for the internal sub-regulator. The recommended valueof CVCC should be no smaller than 1 µF and no greater than10 µF. The capacitor should be a good quality ceramic X5Ror X7R capacitor. In general, a 1 µF ceramic capacitor is rec-ommended for most applications.
SETTING THE START UP TIME (CSS)
The addition of a capacitor connected from the SS pin toground sets the time at which the output voltage will reach thefinal regulated value. Larger values for CSS will result in longerstart up times. Table 3, shown below provides a list of softstart capacitors and the corresponding typical start up times.
TABLE 3. Start Up Times for Different Soft-Start
CapacitorsStart Up Time (ms)
15101520
CSS (nF)none3368100120
30030314
FIGURE 5. Compensation Network for LM20133A good starting value for CC1 for most applictions is 4.7 nF.Once the value of CC1 is chosen the value of RC should becalculated using the equation below to cancel the output filterpole (fP(FIL)) as shown in Figure 4.
A higher crossover frequency can be obtained, usually at theexpense of phase margin, by lowering the value of CC1 andrecalculating the value of RC1. Likewise, increasing CC1 andrecalculating RC1 will provide additional phase margin at alower crossover frequency. As with any attempt to compen-sate the LM20133 the stability of the system should be verifiedfor desired transient droop and settling time.
If the output filter zero, fZ(FIL) approaches the crossover fre-quency (FC), an additional capacitor (CC2) should be placedat the COMP pin to ground. This capacitor adds a pole tocancel the output filter zero assuring the crossover frequencywill occur before the double pole at fSW/2 degrades the phasemargin. The output filter zero is set by the output capacitorvalue and ESR as shown in the equation below.
If different start up times are needed the equation shown be-low can be used to calculate the start up time.
If needed, the value for CC2 should be calculated using theequation shown below.
As shown above, the start up time is influenced by the valueof the Soft-Start capacitor CSS(F) and the 5 µA Soft-Start pincurrent ISS(A). that may be found in the electrical character-istics table.
While the Soft-Start capacitor can be sized to meet many startup requirements, there are limitations to its size. The Soft-Start time can never be faster than 1 ms due to the internaldefault 1 ms start up time. When the device is enabled thereis an approximate time interval of 50 µs when the Soft-Startcapacitor will be discharged just prior to the Soft-Start ramp.If the enable pin is rapidly pulsed or the Soft-Start capacitoris large there may not be enough time for CSS to completelydischarge resulting in start up times less than predicted. Toaid in discharging of Soft-Start capacitor during long disableperiods an external 1 MΩ resistor from SS/TRK to ground canbe used without greatly affecting the start-up time.
USING PRECISION ENABLE AND POWER GOOD
The precision enable (EN) and power good (PGOOD) pins ofthe LM20133 can be used to address many sequencing re-quirements. The turn-on of the LM20133 can be controlledwith the precision enable pin by using two external resistorsas shown in Figure 6.
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Where RESR is the output capacitor series resistance andRC1 is the calculated compensation resistance.
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LM2013330030326
FIGURE 6. Sequencing LM20133 with Precision EnableThe value for resistor RB can be selected by the user to controlthe current through the divider. Typically this resistor will beselected to be between 10 kΩ and 1 MΩ. Once the value forRB is chosen the resistor RA can be solved using the equationbelow to set the desired turn-on voltage.
When designing for a specific turn-on threshold (VTO) the tol-erance on the input supply, enable threshold (VIH_EN), andexternal resistors needs to be considered to insure properturn-on of the device.
The LM20133 features an open drain power good (PGOOD)pin to sequence external supplies or loads and to provide faultdetection. This pin requires an external resistor (RPG) to pullPGOOD high while when the output is within the PGOOD tol-erance window. Typical values for this resistor range from 10kΩ to 100 kΩ.
TRACKING AN EXTERNAL SUPPLY
By using a properly chosen resistor divider network connect-ed to the SS/TRK pin, as shown in Figure 7, the output of theLM20133 can be configured to track an external voltagesource to obtain a simultaneous or ratiometric start up.
30030321
FIGURE 8. Common Start Up Sequences
A simultaneous start up is preferred when powering most FP-GAs, DSPs, or other microprocessors. In these systems thehigher voltage, VOUT1, usually powers the I/O, and the lowervoltage, VOUT2, powers the core. A simultaneous start up pro-vides a more robust power up for these applications since itavoids turning on any parasitic conduction paths that may ex-ist between the core and the I/O pins of the processor.
The second most common power on behavior is known as aratiometric start up. This start up is preferred in applicationswhere both supplies need to be at the final value at the sametime.
Similar to the Soft-Start function, the fastest start up possibleis 1 ms regardless of the rise time of the tracking voltage.When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide sufficient overdriveand transient immunity.
THERMAL CONSIDERATIONS
The thermal characteristics of the LM20133 are specified us-ing the parameter θJA, which relates the junction temperatureto the ambient temperature. Although the value of θJA is de-pendant on many variables, it still can be used to approximatethe operating junction temperature of the device.
To obtain an estimate of the device junction temperature, onemay use the following relationship:
TJ = PDθJA + TA
and
PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR
Where:
TJ is the junction temperature in °C.
PIN is the input power in Watts (PIN = VIN x IIN).
θJA is the junction to ambient thermal resistance for theLM20133.
30030320
FIGURE 7. Tracking an External Supply
Since the Soft-Start charging current ISS is always present onthe SS/TRK pin, the size of R2 should be less than 10 kΩ tominimize the errors in the tracking output. Once a value forR2 is selected the value for R1 can be calculated using ap-propriate equation in Figure 8, to give the desired start up.Figure 8 shows two common start up sequences; the topwaveform shows a simultaneous start up while the waveformat the bottom illustrates a ratiometric start up.
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LM20133TA is the ambient temperature in °C.IOUT is the output load current.
DCR is the inductor series resistance.
It is important to always keep the operating junction temper-ature (TJ) below 125°C for reliable operation. If the junctiontemperature exceeds 160°C the device will cycle in and outof thermal shutdown. If thermal shutdown occurs it is a signof inadequate heatsinking or excessive power dissipation inthe device.
Figure 9, shown below, provides a better approximation of theθJA for a given PCB copper area. The PCB heatsink areaconsists of 2oz. copper located on the bottom layer of the PCBdirectly under the eTSSOP exposed pad. The bottom copperarea is connected to the eTSSOP exposed pad by means ofa 4 x 4 array of 12 mil thermal vias.
30030335
FIGURE 9. Thermal Resistance vs PCB AreaPCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter de-sign. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI,ground bounce, and resistive voltage loss in the traces. Thesecan send erroneous signals to the DC-DC converter resultingin poor regulation or instability.
Good layout can be implemented by following a few simpledesign rules.
1. Minimize area of switched current loops. In a buck regulatorthere are two loops where currents are switched very fast. Thefirst loop starts from the input capacitor, to the regulator VINpin, to the regulator SW pin, to the inductor then out to the
output capacitor and load. The second loop starts from theoutput capacitor ground, to the regulator PGND pins, to theinductor and then out to the load (see Figure 10). To minimizeboth loop areas the input capacitor should be placed as closeas possible to the PVIN pin. Grounding for both the input andoutput capacitor should consist of a small localized top sideplane that connects to PGND and the die attach pad (DAP).The inductor should be placed as close as possible to the SWpin and output capacitor.
2. Minimize the copper area of the switch node. Since theLM20133 has the SW pins on opposite sides of the packageit is recommended to via these pins down to the bottom orinternal layer with 2 to 4 vias on each SW pin. The SW pinsshould be directly connected with a trace that runs across thebottom of the package. To minimize IR losses this traceshould be no smaller that 50 mils wide, but no larger than 100mils wide to keep the copper area to a minimum. In generalthe SW pins should not be connected on the top layer sinceit could block the ground return path for the power ground.The inductor should be placed as close as possible to one ofthe SW pins to further minimize the copper area of the switchnode.
3. Have a single point ground for all device analog groundslocated under the DAP. The ground connections for the com-pensation, feedback, and Soft-Start components should beconnected together then routed to the AGND pin of the de-vice. The AGND pin should connect to PGND under the DAP.This prevents any switched or load currents from flowing inthe analog ground plane. If not properly handled poor ground-ing can result in degraded load regulation or erratic switchingbehavior.
4. Minimize trace length to the FB pin. Since the feedbacknode can be high impedance the trace from the output resistordivider to FB pin should be as short as possible. This is mostimportant when high value resistors are used to set the outputvoltage. The feedback trace should be routed away from theSW pin and inductor to avoid contaminating the feedback sig-nal with switch noise.
5. Make input and output bus connections as wide as possi-ble. This reduces any voltage drops on the input or output ofthe converter and can improve efficiency. If voltage accuracyat the load is important make sure feedback voltage sense ismade at the load. Doing so will correct for voltage drops at theload and provide the best output accuracy.
6. Provide adequate device heatsinking. Use as many vias asis possible to connect the DAP to the power plane heatsink.For best results use a 4x4 via array with a minimum via di-ameter of 12 mils. See the Thermal Considerations section toinsure enough copper heatsinking area is used to keep thejunction temperature below 125°C.
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LM2013330030322
FIGURE 10. Schematic of LM20133 Highlighting Layout Sensitive Nodes
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LM20133Typical Application Circuits
This section provides several application solutions with a billof materials. All bill of materials reference the below figure.
The compensation for these solutions were optimized to workover a wide range of input and output voltages; if a fastertransient response is needed reduce the value of CC1 andcalculate the new value for RC1 as outline in the design guide.
30030301
FIGURE 11.
Bill of Materials (VIN = 5V, VOUT = 3.3V, IOUTMAX = 3A, FSYNC = 750kHz)
Designator
U1CINCOUTLRFCFCVCCRC1CC1CSSRFB1RFB2
Description
Synchronous Buck Regulator47 µF, 1210, X5R, 6.3V47 µF, 1210, X5R, 6.3V
2.5 µH, 10mΩ1Ω, 0603
100 nF, 0603, X7R, 16V1 µF, 0603, X5R, 6.3V
4.99 kΩ, 06033.3 nF, 0603, X7R, 25V33 nF, 0603, X7R, 25V
31.6 kΩ, 060310.2 kΩ, 0603
Part NumberLM20133
GRM32ER60J476ME20GRM32ER60J476ME20
MSS1038-252NLCRCW06031R0J-e3GRM188R71C104KA01GRM188R60J105KA01CRCW06034991F-e3VJ0603Y332KXXAVJ0603Y333KXXACRCW06033162F-e3CRCW06031022F-e3
ManufacturerNational Semiconductor
MurataMurataCoilcraftVishay-DaleMurataMurataVishay-DaleVishay-VitramonVishay-VitramonVishay-DaleVishay-Dale
Qty111111111111
Bill of Materials (VIN = 3.3V or 5V, VOUT = 1.2V, IOUTMAX = 3A, FSYNC = 750kHz)
Designator
U1CINCOUTLRFCFCVCCRC1CC1CSSRFB1RFB2
Description
Synchronous Buck Regulator47 µF, 1210, X5R, 6.3V47 µF, 1210, X5R, 6.3V
2.5 µH, 10mΩ1Ω, 0603
100 nF, 0603, X7R, 16V1 µF, 0603, X5R, 6.3V
2 kΩ, 06034.7 nF, 0603, X7R, 25V33 nF, 0603, X7R, 25V
4.99 kΩ, 060310 kΩ, 0603
Part NumberLM20133
GRM32ER60J476ME20GRM32ER60J476ME20
MSS1038-252NLCRCW06031R0J-e3GRM188R71C104KA01GRM188R60J105KA01CRCW06032001F-e3VJ0603Y472KXXAVJ0603Y333KXXACRCW06034991F-e3CRCW06031002F-e3
ManufacturerNational Semiconductor
MurataMurataCoilcraftVishay-DaleMurataMurataVishay-DaleVishay-VitramonVishay-VitramonVishay-DaleVishay-Dale
Qty111111111111
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LM20133Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead eTSSOP PackageNS Package Number MXA16A
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LM20133Notes
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I
I
I
I
II
LM20133 3A, PowerWise® Synchronous Buck Regulator with Input SynchronizationNotes
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